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Carpal tunnel syndrome (CTS) is a hand disease caused by the pressing of the median nerve present in the palmar side of the wrist. It causes severe pain in the wrist, triggering disturbance during sleep. Different products like splints, braces and gloves are available in the market to alleviate this disease but there was still a need to improve the wearability, comfort and cost of the product. This study was about designing a comfortable and cost-effective wearable system for mild-to-moderate CTS. Transcutaneous electrical nerve stimulation (TENS) therapy has been used to reduce the pain in the wrist.

After simulation by using Proteus software (which allowed the researchers to draw and simulate electrical circuits using ISIS, ARES and PCB design tools virtually), the circuit with optimum frequency, i.e. 33 Hz was selected, and the circuit was developed on a printed circuit board (PCB). The developed circuit was integrated successfully into the half glove structure.

The developed product had good thermophysiological comfort and hand properties as compared to the commercially available product of the same kind. In vivo testing (It involves the testing with living subjects like animals, plants or human beings) was performed which resulted in 85% confirmed viability of the product against CTS. A glove with an integrated circuit was developed successfully to accommodate various sizes without any sex specifications in a cost-effective way to mitigate the issue of CTS.

Industrial workers, individuals frequently using their hands or those diagnosed with CTS may wish to use this product as therapy. The attention could not be paid to the aesthetic or visual appeal of the developed product.

A very comfortable glove with integrated TENS electrodes was developed successfully to accommodate various sizes without any sex specifications in a cost-effective way to mitigate the issues of CTS.

The purpose of this paper is to carry out a detailed analysis of two port converter fed by Solar and wind sources during different operational modes by small signal modelling. The converter is fully characterized and simulated using Matlab/Simulink. The voltage and current waveforms along with their corresponding expressions describing the converter operation are presented in detail. Then the DC-averaged equivalent topology is derived using circuit averaging technique. A complete derivation of the power stage transfer functions relevant to the capacitor voltage loop, such as capacitor voltage to solar voltage and inductor current to wind input voltage is obtained.

Stability analysis is used to analyze the small deviations around the steady-state operating point which helps in modeling the closed loop converter parameters. This paper presents the analysis, modeling and control of two port Cuk-buck converter topology.

Based on the results, a control strategy is designed to manage the energy flow within the system. A lab-level prototype for Cuk-buck converter with PWM controller is implemented and tested under various input conditions to study the performance of the converter during seasonal changes. The simulation and experimental results showed that effective operation and control strategy of the hybrid power supply system managed to be achieved alongside its feasible outputs.

This analysis can be extended to all power electronic converters and will be useful for the design of controllers.

An appropriate control design plays a key role in enhancing the overall performance of the system. Hence, this paper is intended to present in detail the small signal modeling of the Cuk-buck converter along with the control design for all the switching modes.

Though this type of converter topology has been discussed widely in literature, very scarce literature is available related to modeling and control design of the converter. A state-space averaging model of the converter followed by a type-II compensator design is described, and prototype design and experimental results are also presented.

This paper aims to develop high-pass (HP) negative group delay (NGD) investigation based on three-port lumped circuit. The main particularity of the proposed three-port passive topology is the consideration of only a single circuit element represented by a capacitor.

The methodology of the paper is to consider the S-matrix equivalent model derived from admittance matrix approach. So, an S-matrix equivalent model of a three-port circuit topology is established from admittance matrix approach. The frequency-dependent basic expressions are explored to perform the HP-NGD analysis. Then, the existence condition of HP-NGD function type is analytically demonstrated. The specific characteristics and synthesis equations of HP-NGD circuit with respect to the desired optimal NGD value are established.

After computing the frequency expressions to perform the HP-NGD analysis, this study demonstrated the existence condition of HP-NGD function type analytically. The validity of the HP-NGD theory is verified by a prototype of three-port circuit. The proof-of-concept (POC) single capacitor three-port circuit presents an NGD response and characteristics from analytical calculation and simulation is in very good correlation.

An innovative theory of HP-NGD three-port circuit is studied. The proposed HP-NGD topology is constituted by only a single capacitor. After the topological description, the S-matrix model is established from the Y-matrix by means of Kirchhoff voltage law and Kirchhoff current law equations. A POC of single capacitor three-port circuit was designed and simulated with a commercial tool. Then, a prototype with a surface-mounted device component was fabricated and tested. As expected, simulation and measurement results in very good agreement with the calculated model show the feasibility of the HP-NGD behavior. This work is compared to other NGD-type function with diverse number of ports and components.

As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.

Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.

The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.

Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

This paper aims to present the design development and measurement of two aerodynamic slotted X-bands back-to-back planer substrate-integrated rectangular waveguide (SIRWG/SIW) to Microstrip (MS) line transition for satellite and RADAR applications. It facilitates the realization of nonplanar (waveguide-based) circuits into planar form for easy integration with other planar (microstrip) devices, circuits and systems. This paper describes the design of a SIW to microstrip transition. The transition is broadband covering the frequency range of 8–12 GHz. The design and interconnection of microwave components like filters, power dividers, resonators, satellite dishes, sensors, transmitters and transponders are further aided by these transitions. A common planar interconnect is designed with better reflection coefficient/return loss (RL) (S₁₁/S₂₂ ≤ 10 dB), transmission coefficient/insertion loss (IL) (S₁₂/S₂₁: 0–3.0 dB) and ultra-wideband bandwidth on low profile FR-4 substrate for X-band and Ku-band functioning to interconnect modern era MIC/MMIC circuits, components and devices.

Two series of metal via (6 via/row) have been used so that all surface current and electric field vectors are confined within the metallic via-wall in SIW length. Introduced aerodynamic slots in tapered portions achieve excellent impedance matching and tapered junctions with SIW are mitered for fine tuning to achieve minimum reflections and improved transmissions at X-band center frequency.

Using this method, the measured IL and RLs are found in concord with simulated results in full X-band (8.22–12.4 GHz). RLC T-equivalent and p-equivalent electrical circuits of the proposed design are presented at the end.

The measurement of the prototype has been carried out by an available low-cost X-band microwave bench and with a Keysight E4416A power meter in the microwave laboratory.

The transition is fabricated on FR-4 substrate with compact size 14 mm × 21.35 mm × 1.6 mm and hence economical with IL lie within limits 0.6–1 dB and RL is lower than −10 dB in bandwidth 7.05–17.10 GHz. Because of such outstanding fractional bandwidth (FBW: 100.5%), the transition could also be useful for Ku-band with IL close to 1.6 dB.

With the development of integrated circuit and communication technology, digital secure communication has become a research hotspot. This paper aims to design a five-dimensional fractional-order chaotic secure communication circuit with sliding mode synchronous based on microcontroller (MCU).

First, a five-dimensional fractional-order chaotic system for encryption is constructed. The approximate numerical solution of fractional-order chaotic system is calculated by Adomian decomposition method, and the phase diagram is obtained. Then, combined with the complexity and 0–1 test algorithm, the parameters of fractional-order chaotic system for encryption are selected. In addition, a sliding mode controller based on the new reaching law is constructed, and its stability is proved. The chaotic system can be synchronized in a short time by using sliding mode control synchronization.

The electronic circuit is implemented to verify the feasibility and effectiveness of the designed scheme.

It is feasible to realize fractional-order chaotic secure communication using MCU, and further reducing the synchronization error is the focus of future work.

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

This paper aims to find a closed-form expression for the frequency and amplitude of single-ended ring oscillators when transistors experience all regions.

In this paper, the analytical relationships presented for ring oscillator amplitude and frequency are approximately derived due to the nonlinear nature of this oscillator, taking into account the differential equation that governs the ring oscillator and its output waveform.

In the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. The relationship is presented for the frequency, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case.

The validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18 µm technology.

This paper aims to review in-memory computing (IMC) for machine learning (ML) applications from history, architectures and options aspects. In this review, the authors investigate different architectural aspects and collect and provide our comparative evaluations.

Collecting over 40 IMC papers related to hardware design and optimization techniques of recent years, then classify them into three optimization option categories: optimization through graphic processing unit (GPU), optimization through reduced precision and optimization through hardware accelerator. Then, the authors brief those techniques in aspects such as what kind of data set it applied, how it is designed and what is the contribution of this design.

ML algorithms are potent tools accommodated on IMC architecture. Although general-purpose hardware (central processing units and GPUs) can supply explicit solutions, their energy efficiencies have limitations because of their excessive flexibility support. On the other hand, hardware accelerators (field programmable gate arrays and application-specific integrated circuits) win on the energy efficiency aspect, but individual accelerator often adapts exclusively to ax single ML approach (family). From a long hardware evolution perspective, hardware/software collaboration heterogeneity design from hybrid platforms is an option for the researcher.

IMC’s optimization enables high-speed processing, increases performance and analyzes massive volumes of data in real-time. This work reviews IMC and its evolution. Then, the authors categorize three optimization paths for the IMC architecture to improve performance metrics.

The purpose of this study is to propose an extended reliability method for an industrial motor drive by integrating the physics of failure (PoF).

Industrial motor drive systems (IMDS) are currently expected to perform beyond the desired operating conditions to meet the demand. The PoF of the subsystem affects its reliability under such harsh operating circumstances. It is crucial to estimate reliability by integrating PoF, which helps in understanding its impact and to develop a fault-tolerant design, particularly in such an integrated drive system. An integrated PoF extended reliability method for industrial drive system is proposed to address this issue. In research, the numerical failure rate of each component of industrial drive is obtained first with the help of the MIL-HDBK-217 military handbook. Furthermore, the mathematically deduced proposed approach is modeled in the GoldSim Monte Carlo reliability workbench.

From the results, for a 15% rise in integrated PoF, the reliability and availability of the entire IMDS dropped by 23%, resulting in an impact on mean time to failure (MTTF).

The integrated PoF of the motor and motor controller affects industrial drive reliability, which falls to 0.18 with the least MTTF (2.27 years); whose overall reliability of industrial drive drops to 0.06 if it is additionally integrated with communication protocol.