Search results

The purpose of this study was to identify the key third-party logistics (3PL) selection criteria for the integrated circuit (IC) manufacturing industry in Taiwan. The IC manufacturing industry seeks global sourcing, and is facing increasing pressure due to fierce market competition. More than a cost reduction strategy, 3PL is a strategic tool for IC manufacturers to gain a competitive advantage in a global supply chain complex.

The triangulation method that combines qualitative and quantitative approaches was used in the study. The qualitative approach of focus group discussions was adopted to establish the decision framework, and the quantitative approach of the analytic hierarchy process was used to explore the relative importance of the 3PL selection criteria. Finally, an in-depth proof-by-example interview was undertaken to provide an insightful interpretation of the research results.

The research shows that performance is the most important criterion group, followed by cost, service, quality assurance, intangible and information technology. At the detailed sub-criteria level, document accuracy, problem-solving capability, continuous cost reduction, value-added services and associated cost control capability are the top five criteria.

This study focused on the IC manufacturing sector in Taiwan. Multi-country and multi-industry studies are recommended to help further validate and generalise the research findings.

Due to its application of triangulation, this study is a pioneering work on the 3PL selection criteria in a high-tech manufacturing industry. Furthermore, the value of this research is that it enhances the body of knowledge of 3PL selection by identifying certain emerging selection criteria, it could serve as a guideline for IC manufacturers in planning logistics outsourcing actions and it could significantly contribute to the efforts of 3PL providers in evaluating whether they comply with customer needs and adhere to core competency development.

The purpose of this paper is to review and explore the evolution, advances and future trends of cloud manufacturing, placing the focus on the quality of services. Moreover, moving toward the new trend of cyber-physical systems (CPS), a cloud-based cyber-physical system (CBCPS) is proposed combining the key enabling techniques of this decade, namely Internet of Things (IoT), cloud computing, Big Data analytics and CPS.

First, an extensive review is made on cloud computing and its applications in manufacturing sectors, namely product development, manufacturing processes and manufacturing systems management. Second, a conceptual CBCPS which combines key enabling techniques including cloud computing, CPS and IoT is proposed. Finally, a review on the quality of the services (QoS) presented in the second step, along with the main security issues of cloud manufacturing, is conducted.

The findings of this review indicate that the combination of the key enabling techniques presented in the CBCPS will lead to a new manufacturing paradigm capable of facing the new challenges and trends. The opportunities, as well as the challenges and barriers of the proposed framework are presented, concluding that the transition into this whole new era of networked computing and manufacturing has a valuable impact, but also generates several security and quality issues.

The paper is the first to specifically study the QoS as a factor in the proposed manufacturing paradigm.

This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications.

More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs).

Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding.

This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

The purpose of this study is to formulate a new class of vehicle routing problem with an objective to minimise the total cost of raw material collection and derive a new approach to solve optimization problems. This study can help to select the optimum number of suppliers based on cost.

To model the raw material vehicle routing problem, a mixed integer linear programming (MILP) problem is formulated. An interesting phenomenon added to the proposed problem is that there is no compulsion to visit all suppliers. To guarantee the demand of semiconductor industry, all visited suppliers should reach a given raw material capacity requirement. To solve the proposed model, the authors developed a novel hybrid approach that is a combination of block and edge recombination approaches. To avoid bias, the authors compare the results of the proposed methodology with other known approaches, such as genetic algorithms (GAs) and ant colony optimisation (ACO).

The findings indicate that the proposed model can be useful in industries, where multiple suppliers are used. The proposed hybrid approach provides a better sequence of suppliers compared to other heuristic techniques.

The data used in the proposed model is generated based on previous literature. The problem derives from the assumption that semiconductor industries use a variety of raw materials.

This study provides a new model and approach that can help practitioners and policymakers select suppliers based on their logistics costs.

This study provides two important contributions in the context of the supply chain. First, it provides a new variant of the vehicle routing problem in consideration of raw material collection; and second, it provides a new approach to solving optimisation problems.

Organisations increasingly rely on information being processed and communicated, and whether the processing is undertaken by personal computers, mainframes, minicomputers, private automatic branch exchanges (PABXs) or voice messaging systems, the communication is invariably by means of a cable. And since organisations have always sought to undertake activities more efficiently — however they have variously described efficiency — the result is that systems, ideally, are used more continuously. Technologists are responding to the challenge of integrating systems.

The purpose of this paper is to focus on the accurate and steady control on trajectory tracking for wafer transfer robot, suppress the vibration and reduce the contour error.

The wafer transfer robot dynamic model is modeled. Through analyzing the characteristics of wafer transfer robot, cross‐coupled synchronized control is proposed based on the contour error model in task space to improve synchronization of the joints; the shaping for the joints by input shaper in task space is applied to suppress the vibration of the end effector during trajectory tracking. Then combining the cross‐coupled synchronized control with input shaping is proposed to improve accuracy and suppress the vibration.

The combination of cross‐coupled synchronized control and input shaping control method can improve the contour accuracy and reduce the vibration simultaneously during trajectory tracking. And the control method can be used to control the trajectory of wafer transfer robot.

The transfer station is in the center of the robot body. When the transfer station may deviate from the center of the robot body, the synchronizing performance of three axes on the same plane must be considered.

The proposed method can be used to solve the vibration and synchronizing performance problems on similar SCARA robots in semi‐conductor and liquid crystal display industry.

The proposed control method takes advantage of the cross‐coupled synchronized control and input shaping control method. This combination has improved contour accuracy and reduced vibration than applying other methods, and it has achieved better performance than using single one control method only.

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

The purpose of this paper is to present a hybrid manufacturing system that integrates stereolithography (SL) and direct print (DP) technologies to fabricate three‐dimensional (3D) structures with embedded electronic circuits. A detailed process was developed that enables fabrication of monolithic 3D packages with electronics without removal from the hybrid SL/DP machine during the process. Successful devices are demonstrated consisting of simple 555 timer circuits designed and fabricated in 2D (single layer of routing) and 3D (multiple layers of routing and component placement).

A hybrid SL/DP system was designed and developed using a 3D Systems SL 250/50 machine and an nScrypt micro‐dispensing pump integrated within the SL machine through orthogonally‐aligned linear translation stages. A corresponding manufacturing process was also developed using this system to fabricate 2D and 3D monolithic structures with embedded electronic circuits. The process involved part design, process planning, integrated manufacturing (including multiple starts and stops of both SL and DP and multiple intermediate processes), and post‐processing. SL provided substrate/mechanical structure manufacturing while interconnections were achieved using DP of conductive inks. Simple functional demonstrations involving 2D and 3D circuit designs were accomplished.

The 3D micro‐dispensing DP system provided control over conductive trace deposition and combined with the manufacturing flexibility of the SL machine enabled the fabrication of monolithic 3D electronic structures. To fabricate a 3D electronic device within the hybrid SL/DP machine, a process was developed that required multiple starts and stops of the SL process, removal of uncured resin from the SL substrate, insertion of active and passive electronic components, and DP and laser curing of the conductive traces. Using this process, the hybrid SL/DP technology was capable of successfully fabricating, without removal from the machine during fabrication, functional 2D and 3D 555 timer circuits packaged within SL substrates.

Results indicated that fabrication of 3D embedded electronic systems is possible using the hybrid SL/DP machine. A complete manufacturing process was developed to fabricate complex, monolithic 3D structures with electronics in a single set‐up, advancing the capabilities of additive manufacturing (AM) technologies. Although the process does not require removal of the structure from the machine during fabrication, many of the current sub‐processes are manual. As a result, further research and development on automation and optimization of many of the sub‐processes are required to enhance the overall manufacturing process.

A new methodology is presented for manufacturing non‐traditional electronic systems in arbitrary form, while achieving miniaturization and enabling rugged structure. Advanced applications are demonstrated using a semi‐automated approach to SL/DP integration. Opportunities exist to fully automate the hybrid SL/DP machine and optimize the manufacturing process for enhancing the commercial appeal for fabricating complex systems.

This work broadly demonstrates what can be achieved by integrating multiple AM technologies together for fabricating unique devices and more specifically demonstrates a hybrid SL/DP machine that can produce 3D monolithic structures with embedded electronics and printed interconnects.

The increase in semiconductor integration level has led to complex Integrated Circuits (ICs) characterised by an increasing number of I/O, such that dies with 40 to 84 metallised pads are currently manufactured and frequently used in modern electronic systems. The advent from 1980 onwards of these LSI‐VLSI semiconductors requires new economical micropackages to be devised that can be adapted to surface mounting techniques on Hybrid Integrated Circuits (HICs) and Printed Circuits Boards (PCBs). Plastic encapsulation using a transfer moulded epoxy resin is a widely used method for packaging silicon devices because of the reduced manufacturing cost for large volumes. This economic criterion, which is considered with widespread interest in the electronics industry, has recently led the major semiconductor manufacturers to produce Plastic Leaded Chip Carriers (PLCCs) with up to 84 J bend connections on 1·27 mm pitch, and Mini Quad Packs with 40 to 84 Z bend pins on 0·75∼0·80mm centres. However, until now, a significant number of ICs, such as full custom circuits, are not yet available in any packaged form. Thus, in order to take advantage of the compactness offered by micropackages without being under component manufacturers' constraints for packaged LSI needs, it was decided at the Microelectronics Division of CIT‐Alcatel to develop a flexible semiconductor encapsulation technology which does not require any moulding equipment. The process involved has led to the development of a small economical package with 52 peripheral Z bend leads on 0·75 mm centres which has been evaluated. This original LSI carrier, named Plastic Composite Package (PCP) because of its special feature, is perfectly suited to the specific needs of multilayer HICs for all non‐military applications. In addition, another PCP format with 68 pins on 0·635 mm centres, designed for LSI Industrial applications, has been investigated. The purpose of this paper is to explain the specific needs in the hybrid industry and to give the authors' views on trends in LSI‐VLSI plastic encapsulation. Moreover, the PCP manufacturing process is described, the evaluation results being discussed as well as the economic aspect.

The purpose of this paper is to form copper coin-embedded printed circuit board (PCB) for high heat dissipation.

Manufacturing optimization of copper coin-embedded PCB involved in the design and treatment of copper coin, resin flush removal and flatness control. Thermal simulation was used to investigate the effect of copper coin on heat dissipation of PCB products. Lead-free reflow soldering and thrust tests were used to characterize the reliable performance of copper coin-embedded PCB.

The copper coin-embedded PCB had good agreement with resin flush removal and flatness control. Thermal simulation results indicated that copper coin could significantly enhance the heat-dissipation rate by means of a direct contact with the high-power integrated circuit chip. The copper coin-embedded PCB exhibited a reliable structure capable of withstanding high-temperature reflow soldering and high thrust testing.

The use of a copper coin-embedded PCB could lead to higher heat dissipation for the stable performance of high-power electronic components. The copper coin-embedded method could have important potential for improving the design for heat dissipation in the PCB industry.