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The purpose of this paper is to review traditional hermeticity test methods when applied to typical micro‐electro‐mechanical systems (MEMS) cavity volumes and to propose potential solutions.

Standards for traditional testing have been applied to typical MEMS cavity volumes and the resulting issues of range and sensitivity discussed. In situ test structures have been designed and fabricated with access to the internal cavities to allow characterisation of the structures as a function of pressure.

The ultra low leak rates necessary to guarantee hermeticity of MEMS cannot be measured using traditional methods. Optical test methods are possible although in situ test structures currently provide the greatest sensitivity. A portfolio of test techniques is required to allow accurate hermeticity testing of MEMS.

This paper provides a starting point for further investigation into several methods of MEMS hermeticity testing.

This paper provides a review of the limitations of traditional testing and proposals for future testing as the trend towards smaller volume packaging continues.

Additive manufacturing (AM) is readily capable of producing models and prototypes of complex geometry and is advancing in creating functional parts. However, AM processes typically underperform traditional manufacturing methods in mechanical properties, surface roughness and hermeticity. Solvent vapor treatments (vapor polishing) are commonly used to improve surface quality in thermoplastic parts, but the results are poorly characterized.

This work quantifies the surface roughness change and also evaluates the effect on hermeticity and mechanical property impacts for “as-printed” and acetone vapor-polished ABS tensile specimens of 1-, 2- and 4-mm thicknesses produced by material extrusion (FDM).

Vapor polishing proves to decrease the power spectral density for surface roughness features larger than 20 µm by a factor of 10× and shows significant improvement in hermeticity based on both perfluorocarbon gross leak and pressure leak tests. However, there is minimal impact on mechanical properties with the thin specimens showing a slight increase in elongation at break but decreased elastic modulus. A bi-exponential diffusion decay model for solvent evaporation suggest a thickness-independent and thickness-dependent time constant with the latter supporting a plasticizing effect on mechanical properties.

The contributions of this work show vapor polishing can have a substantial impact on the performance for end-use application of ABS FDM components.

Due to oxide formation at the die backside, excessive non‐wetting and voiding can occur especially for the larger die (100K sq. mil) by gold eutectic die attach. Such voiding can cause die lift‐off and cracking. Ag/glass seems to be a promising candidate. However, it has some shortcomings. First, solder seal hermeticity reject may occur due to nickel diffusing through gold metallisation and being oxidised on the surface of the multilayer package. Secondly, for those devices requiring backside contact, gold metallisation on the die backside becomes the barrier for the reaction between the silicon and the glass. The adhesion may be degraded. The factors which may overcome these shortcomings will be discussed.

The challenge presented by advanced package development in the past five years has further accentuated the constant need for package quality and reliability monitoring through extensive laboratory testing and evaluation. As pin counts and chip geometries have continued to increase, there has been additional pressure from the military and commercial sectors to improve interconnect designs for packaged chips, including chips directly attached to the printed wiring board (PWB). One of the options employed has been tape automated bonding (TAB). However, this assembly technique also presents new standardisation, qualification and reliability problems. Therefore, at Rome Air Development Center (RADC), there is regular assessment (through in‐house failure analysis studies) of parts destined for military and space systems. In addition, Department of Defense (DoD) high tech development programmes, such as very high speed integrated circuits (VHSIC), have utilised all present screening methods for package evaluation, and have addressed the need for development of more definitive non‐destructive tests. To answer this need, two RADC contractual efforts were awarded on laser thermal and ultrasonic inspection techniques. Through these package evaluations, a number of potential reliability problems are identified and the results provided to the specific contractors for corrective action implementation. Typical problems uncovered are lid material and pin corrosion, damage to external components and adhesion problems between copper leads and polyimide supports, hermeticity failures, high moisture content in sealed packages and particle impact noise detection (PIND) test failures (internal particles). Further tests uncover bond strength failures, bond placement irregularities, voids in die attach material (potential heat dissipation problems), and die surface defects such as scratches and cracks. This presentation will review the specific package level physical test methods that are employed as a means of evaluating reliable package performance. Many of the tests, especially the environmental tests—e.g., salt atmosphere and moisture resistance—provide accelerated forms of anticipated conditions and are therefore applied as destructive tests to assess package quality and reliability in field use. In addition to a manufacturer's compliance with designated qualification procedures, the key to package quality lies in utilising good materials and well‐controlled assembly techniques. This practice, along with effective package screen tests, will ensure reliable operation of very large scale integration (VLSI) devices in severe military and commercial environment applications.

A critical analysis of packaging and sealing methods for integrated circuits, hybrid microcircuits and multichip modules has been done. The best hermetic and high yield weld seal is examined along with other conventional seals like solder seal, frit seal and plastic seal with special emphasis on materials and processes involved in each case. An overview of emerging technology is also presented. A comparative analysis is made for selection of the right technology and material for a particular requirement.

The drive towards low unit cost in optoelectronics packaging is assisted by simple, rapid assembly processes, and by avoiding the need for hermeticity. This paper discusses the use of visible blue‐light cured resins as an important issue in assembly techniques. Results are also reported on trials of silicone gels as a means to produce hermetic equivalence performance in optoelectronic (O‐E) components and associated electronics. Photodiodes coated in these gels could be expected to have a service life of >60 years and results for coated lasers are encouraging with degradations of 4%/1000 h of damp heat stress, while GaAs ICs showed no degradation. The potential of these technologies has made possible the fabrication of a simple photodiode mount with coupling efficiencies approaching 100%. Low cost laser assembly has also been investigated. To demonstrate the feasibility of these technologies an O‐E transceiver module has been produced.

This paper describes some of the benefits of electronic packages manufactured from silicon carbide reinforced aluminium composites. The housings which were analysed and tested consisted of iron‐nickel alloy sidewalls soldered to composite bases. The metal matrix composite bases were produced using Lanxide's PRIMEX™ pressureless metal infiltration process. Hermeticity test results on the base to sidewall seals are presented along with comparative electrical performance of the composite versus conventional base materials. Analysis of the thermal, mechanical and weight performance of this approach is also provided.

To meet the hybrid industry's growing need for low‐cost, high‐reliability, high‐density multilayer circuitry, the authors' company has developed a non‐warp, hermetic, non‐battery effect, crystallising dielectric for use with gold (Au) and silver (Ag) ‐based conductors. The crystallising nature of the dielectric, together with the use of glasses which do not contain highly mobile ions, ensures high dielectric Ag‐migration resistance. The crystalline structure of the dielectric also has the advantage of ensuring excellent solderability and bondability of top conductors. This paper will deal with the most important theoretical considerations when developing such a dielectric, together with its main properties and advantages. The results are supported by graphs and diagrams showing the properties of this new material.

The recently developed Reduced Oxide Soldering Activation (ROSA™) method is shown to be compatible with long‐term use with mass soldering processes. Prototype regeneration cells operated for as long as six months with minimal maintenance retained their effectiveness for providing short wetting times under a variety of perturbations. The operating window for the process is wide and component degradation caused by exposure to the fully charged solution is minimal. The ROSA treatment provides soldering performance comparable to that attainable with a fully activated rosin flux and offers the promise of providing low soldering defect rates without the use of CFC solvents.

Low temperature cofiring ceramic tape (LTCC) is increasingly used for the production of complex three‐dimensional multilayer interconnect structures in microelectronics packaging. LTCC technology offers many attractive features including mechanical strength, high temperature performance, hermeticity and, with advanced crystallisable ceramic compositions, such as the Ferro A6 tape, outstanding microwave performance. Key among properties that discriminate LTCC technology from competing packaging approaches are two features that allow both design flexibility and maximum integratability: the ability to integrate the full range of passive components — resistors, capacitors and inductors — within the monolithic LTCC structure: and the fact that the LTCC interconnect system provides not only the interchip connection but also the package itself for the components, that is, the LTCC does not have to be placed in a further level of packaging before use. In this paper, the flexibility of design achievable with this company's A6 tape system including integratable passive components is discussed. Design rules that should be observed with the system to ensure that maximum benefit can be obtained from the key performance characteristics of the LTCC materials are addressed. Data supporting these design considerations are presented, as is a review of production processing parameters and their effect on yield, performance and cost of modules produced using the system. Specific project examples are reviewed to demonstrate the applications of this technology in advanced packaging design.