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This paper aims to analyze the morphology transformation on the Cu₃Sn grains during the formation of full Cu₃Sn solder joints in electronic packaging.

Because of the infeasibility of analyzing the morphology transformation intuitively, a novel equivalent method is used. The morphology transformation on the Cu₃Sn grains, during the formation of full Cu₃Sn solder joints, is regarded as equivalent to the morphology transformation on the Cu₃Sn grains derived from the Cu/Sn structures with different Sn thickness.

During soldering, the Cu₃Sn grains first grew in the fine equiaxial shape in a ripening process until the critical size. Under the critical size, the Cu₃Sn grains were changed from the equiaxial shape to the columnar shape. Moreover, the columnar Cu₃Sn grains could be divided into different clusters with different growth directions. With the proceeding of soldering, the columnar Cu₃Sn grains continued to grow in a feather of the width growing at a greater extent than the length. With the growth of the columnar Cu₃Sn grains, adjacent Cu₃Sn grains, within each cluster, merged with each other. Next, the merged columnar Cu₃Sn grains, within each cluster, continued to merge with each other. Finally, the columnar Cu₃Sn grains, within each cluster, merged into one coarse columnar Cu₃Sn grain with the formation of full Cu₃Sn solder joints. The detailed mechanism, for the very interesting morphology transformation, has been proposed.

Few researchers focused on the morphology transformation of interfacial phases during the formation of full intermetallic compounds joints. To bridge the research gap, the morphology transformation on the Cu₃Sn grains during the formation of full Cu₃Sn solder joints has been studied for the first time.

This paper used a novel technique, which is thermo-compression bonding, and Sn-1.0Ag-0.5Cu solder to form a full intermetallic compound (IMC) Cu₃Sn joints (Cu/Cu₃Sn/Cu joints). The purpose of the study is to form high-melting-point IMC joints for high-temperature power electronics applications. The study also investigated the effect of temperature gradient on the microstructure evolution and the growth behavior of IMCs.

In this paper, the thermo-compression bonding technique was used to form full Cu₃Sn joints.

Experimental results indicated that full Cu/Cu3Sn/Cu solder joints with the thickness of about 5-6 µm are formed in a short time of 9.9 s and under a low pressure of 0.016 MPa at 450°C by thermo-compression bonding technique. During the bonding process, Cu₆Sn₅ grew with common scallop-like shape at Cu/SAC105 interfaces, which was followed by the growth of Cu₃Sn with planar-like shape between Cu/Cu6Sn5 interfaces. Meanwhile, the morphology of Cu₃Sn transformed from a planar-like shape to wave-like shape until full IMCs solder joints were eventually formed during thermo-compression bonding process. Asymmetrical growth behavior of the interfacial IMCs was also clearly observed at both ends of the Cu/SAC105 (Sn-1.0Ag-0.5Cu)/Cu solder joints. Detailed reasons for the asymmetrical growth behavior of the interfacial IMCs during thermo-compression bonding process are given. The compound of Ag element causes a reduction in Cu dissolution rate from the IMC into the solder solution at the hot end, inhibiting the growth of IMCs at the cold end.

This study used the thermo-compression bonding technique and Sn-1.0Ag-0.5Cu to form full Cu₃Sn joints.

This study aims to analyze the shear strength and fracture mechanism of full Cu-Sn IMCs joints with different Cu₃Sn proportion and joints with the conventional interfacial structure in electronic packaging.

The Cu-Sn IMCs joints with different Cu₃Sn proportion were fabricated through soldering Cu-6 μm Sn-Cu sandwich structure under the extended soldering time and suitable pressure. The joints of conventional interfacial structure were fabricated through soldering Cu-100 μm Sn-Cu sandwich structure. After the shear test was conducted, the fracture mechanism of different joints was studied through observing the cross-sectional fracture morphology and top-view fracture morphology of sheared joints.

The strength of joints with the conventional interfacial structure was 26.6 MPa, while the strength of full Cu-Sn IMCs joints with 46.7, 60.6, 76.7 and 100 per cent Cu₃Sn was, respectively, 33.5, 39.7, 45.7 and 57.9 MPa. The detailed reason for the strength of joints showing such regularity was proposed. For the joint of conventional interfacial structure, the microvoids accumulation fracture happened within the Sn solder. However, for the full Cu-Sn IMCs joint with 46.7 per cent Cu₃Sn, the cleavage fracture happened within the Cu6Sn5. As the Cu₃Sn proportion increased to 60.6 per cent, the inter-granular fracture, which resulted in the interfacial delamination of Cu₃Sn and Cu6Sn5, occurred along the Cu₃Sn/Cu6Sn5 interface, while the cleavage fracture happened within the Cu6Sn5. Then, with the Cu₃Sn proportion increasing to 76.7 per cent, the cleavage fracture happened within the Cu6Sn5, while the transgranular fracture happened within the Cu₃Sn. The inter-granular fracture, which led to the interfacial delamination of Cu₃Sn and Cu, happened along the Cu/Cu₃Sn interface. For the full Cu₃Sn joint, the cleavage fracture happened within the Cu₃Sn.

The shear strength and fracture mechanism of full Cu-Sn IMCs joints was systematically studied. A direct comparison regarding the shear strength and fracture mechanism between the full Cu-Sn IMCs joints and joints with the conventional interfacial structure was conducted.

This study aims to analyse the changes in the microstructure and grain orientation of the full Cu₃Sn solder joint (Cu/Cu₃Sn/Cu) during isothermal aging at 420°C.

The Cu₃Sn solder joint was fabricated through soldering Cu/Sn/Cu structure and then aged at 420°C. The microstructure evolution and grain orientation were studied by observing the cross-section and top-view surfaces of solder joints.

Original Cu₃Sn solder joint initially transformed into the full Cu₄₁Sn₁₁solder joint (Cu/Cu₄₁Sn₁₁/Cu) at 10 h and finally into the full α(Cu) solder joint (Cu/α(Cu)/Cu) at 150 h during aging. Micro-voids formed in the center of the solder joint interface during the conversion of Cu₄₁Sn₁₁to α(Cu), resulting in lower reliability of the solder joint. Cu₃Sn and Cu₄₁Sn₁₁ grains presented a column-like shape, while α(Cu) presented an irregular shape. The average grain sizes of interfacial phases first increased and then decreased during aging. Original Cu₃Sn solder joint exhibited two main textures: [100]//TD and [203]//TD. For Cu₄₁Sn₁₁, the preferred orientation of [111]//TD was found in the early nucleation stage, while the orientation of the formed full Cu₄₁Sn₁₁ solder joint was dispersed. Furthermore, α(Cu) grains exhibited {100}<100> preferred orientation.

Few researchers focused on the process of microstructure and grain orientation changes during high-temperature (> 300°C) aging of Cu₃Sn solder joint. To bridge the research gap, a high-temperature aging experiment was conducted on Cu₃Sn solder joints.

This paper introduces a series of eight describing the research work undertaken into the most pervasive of quality assurance problems in the mass soldering of plated‐through‐hole (PTH) printed circuit boards, namely the occurrence of voids and blowholes in the solder fillets. The research programme has been carried out at NPL with advice and practical involvement of members of the Soldering Science and Technology Club whose contributions have played a large part in its successful outcome. The work has led to an understanding of the mechanisms giving rise to this problem and recommendations for production procedures to fully control it. In this first paper, results are presented of a UK‐wide survey of the electronics assembly industry and of the assessment made regarding the extent, the harmfulness and the cost of the problem of voids and blowholes.

One concern that has slowed the progress of surface mounted technology, in particular leadless chip carriers, has been the question of the reliability of the surface mount attachment technology. This concern follows from the realisation that the functional reliability of surface mount technology is a very complex issue involving many not very well understood components. What is needed is a relatively simple, useful, predictive model. The model reported here sidesteps the numerous complex underlying issues, which, if considered separately, make a predictive reliability model all but impossible, by taking a purely phenomenological approach and relegating second‐order effects to a lumped empirical figure of merit.

This paper aims to present a machine learning framework for using big data analytics to predict the reliability of solder joints. The purpose of this study is to accurately predict the reliability of solder joints by using big data analytics.

A machine learning framework for using big data analytics is proposed to predict the reliability of solder joints accurately.

A machine learning framework for predicting the life of solder joints accurately has been developed in this study. To validate its accuracy and efficiency, it is applied to predict the long-term reliability of lead-free Sn96.5Ag3.0Cu0.5 (SAC305) for three commonly used surface finishes such OSP, ENIG and IAg. The obtained results show that the predicted failure based on the machine learning method is much more accurate than the Weibull method. In addition, solder ball/bump joint failure modes are identified based on various solder joint failures reported in the literature.

The ability to predict thermal fatigue life accurately is extremely valuable to the industry because it saves time and cost for product development and optimization.

Automotive electronics, after 1995, will be similar to aerospace electronics because there is a demand for low weight and volume together with very high speed and ultra‐high reliability. What is different is that automotive electronics must achieve all those properties at very low cost. It will be shown that when using ASIC chips the chip area is determined by the number of pins instead of the number of components of the active circuit. As ASIC technology proceeds towards line widths in the submicrometre range, the ratio of active Si area to total chip area is becoming much less than 1. This means that on the ASIC chip there is Si area which is ‘empty’. This ‘empty’ Si area can be used for designing self‐test circuits and redundant functions on the ASIC chip at a cost penalty slightly higher than the design cost. It will also be shown that these ASICs can work in the order of 100 MHz at the chip level. Such ASIC chips will therefore have a very high reliability at the chip level due to the inherent properties of the Si and the built‐in redundancy. At the same time they can work at very high speed. From a performance point of view the best solution should be a highly miniaturised packaging technology. With self‐test circuits on the chip, there is a good correlation between wafer test and final test. Therefore, from an economical point of view, working with chips will then have an economical advantage compared with working with packaged circuits. From a reliability point of view it will be shown that the solder joints are the limiting factor. A critical review is presented of the reliability problems plaguing the SMD and soldering technology of today. It will be shown that, if SMD technology is to meet the reliability demands in a future automotive environment, it will have to have solder joint failure rates better than 30 ppm over the life, 17 years, in automotive applications. The conclusion is that a multi‐ASIC chip approach has the best potential as the solution for the future, post 1995, automotive electronics, provided there is a highly reliable chip interconnection technology available at that time.

In an electronic manufacturing environment, rework of pin‐in‐hole components on printed circuit boards is an essential process. Rework enhances product yield and through‐put efficiency by allowing device repair to occur quickly and at significantly reduced costs in comparison with complete board reconstruction. However, current rework techniques are not without their shortcomings, most notably enhanced dissolution of copper in plated‐through holes. This paper discusses a new methodology using polymer films as barrier layers, resulting in negligible plated‐through‐hole copper dissolution when conventional rework technologies are practised.

Tape automated bonding (TAB) is a powerful technique for connecting fine‐pitch integrated components to the corresponding substrates. This paper describes the specific example of hot‐bar soldering TAB components with an outer lead bonding (OLB) pitch of 0.150 mm to FR‐4 printed wiring boards. The prerequisites to be taken into account, the outer lead bonding process parameters, the hot‐bar soldering results and recommendations are presented.