Search results

The conventional design method relies on a priori knowledge, which limits the rapid and efficient development of electronic packaging structures. The purpose of this study is to propose a hybrid method of data-driven inverse design, which couples adaptive surrogate model technology with optimization algorithm to to enable an efficient and accurate inverse design of electronic packaging structures.

The multisurrogate accumulative local error-based ensemble forward prediction model is proposed to predict the performance properties of the packaging structure. As the forward prediction model is adaptive, it can identify respond to sensitive regions of design space and sample more design points in those regions, getting the trade-off between accuracy and computation resources. In addition, the forward prediction model uses the average ensemble method to mitigate the accuracy degradation caused by poor individual surrogate performance. The Particle Swarm Optimization algorithm is then coupled with the forward prediction model for the inverse design of the electronic packaging structure.

Benchmark testing demonstrated the superior approximate performance of the proposed ensemble model. Two engineering cases have shown that using the proposed method for inverse design has significant computational savings while ensuring design accuracy. In addition, the proposed method is capable of outputting multiple structure parameters according to the expected performance and can design the packaging structure based on its extreme performance.

Because of its data-driven nature, the inverse design method proposed also has potential applications in other scientific fields related to optimization and inverse design.

This paper focuses on the fluid-structure interaction (FSI) analysis of moisture induced stress for the flip chip ball grid array (FCBGA) package with hydrophobic and hydrophilic materials during the reflow soldering process. The purpose of this paper is to analyze the influence of moisture concentration and FCBGA with hydrophobic material on induced pressure and stress in the package at varies times.

The present study analyzed the warpage deformation during the reflow process via visual inspection machine (complied to Joint Electron Device Engineering Council standard) and FSI simulation by using ANSYS/FLUENT package. The direct concentration approach is used to model moisture diffusion and ANSYS is used to predict the Von-Misses stress. Models of Test Vehicle 1 (similar to Xie et al., 2009b) and Test Vehicle 2 (FCBGA package) with the combination of hydrophobic and hydrophilic materials are performed. The simulation for different moisture concentrations with reflows process time has been conducted.

The results from the mechanical reliability study indicate that the FSI analysis is found to be in good agreement with the published study and acceptable agreement with the experimental result. The maximum Von-Misses stress induced by the moisture significantly increased on FCBGA with hydrophobic material compared to FCBGA with a hydrophilic material. The presence of hydrophobic material that hinders the moisture desorption process. The analysis also illustrated the moisture could very possibly reside in electronic packaging and developed beyond saturated vapor into superheated vapor or compressed liquid, which exposed electronic packaging to higher stresses.

The findings provide valuable guidelines and references to engineers and packaging designers during the reflow soldering process in the microelectronics industry.

Studies on the influence of moisture concentration and hydrophobic material are still limited and studies on FCBGA package warpage under reflow process involving the effect of hydrophobic and hydrophilic materials are rarely reported. Thus, this study is important to effectively bridge the research gap and yield appropriate guidelines in the microelectronics industry.

As the solution to improve fatigue life and mechanical reliability of packaging structure, the material selection in PCB stack-up and partitioning design on PCB to eliminate the electromagnetic interference by keeping all circuit functions separate are suggested to be optimized from the mechanical stress point of view.

The present paper investigated the effect of RO4350B and RT5880 printed circuit board (PCB) laminates on fatigue life of the QFN (quad flat no-lead) packaging structure for high-frequency applications. During accelerated thermal cycling between −50 °C and 100 °C, the mismatched coefficients of thermal expansion (CTE) between packaging and PCB materials, initial PCB warping deformation and locally concentrated stress states significantly affected the fatigue life of the packaging structure. The intermetallics layer and mechanical strength of solder joints were examined to ensure the satisfactorily soldering quality prior to the thermal cycling process. The failure mechanism was investigated by the metallographic observations using a scanning electron microscope.

Typical fatigue behavior was revealed by grain coarsening due to cyclic stress, while at critical locations of packaging structures, the crack propagations were confirmed to be accompanied with coarsened grains by dye penetration tests. It is confirmed that the cyclic stress induced fatigue deformation is dominant in the deformation history of both PCB laminates. Due to the greater CTE differences in the RT5880 PCB laminate with those of the packaging materials, the thermally induced strains among different layered materials were more mismatched and led to the initiation and propagation of fatigue cracks in solder joints subjected to more severe stress states.

In addition to the electrical insulation and thermal dissipation, electronic packaging structures play a key role in mechanical connections between IC chips and PCB.

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.

High silicon Si–Al alloys (50–70 wt% Si) have been developed by Osprey Metals Ltd for use in electronic packaging. They have the advantages of a coefficient of thermal expansion that can be tailored to match ceramics and electronic materials (6–11 ppm/K), low density (<2.8 g/cm³) high thermal conductivity (>100 W/m K). These alloys are also environmentally friendly and are easy to recycle.These Osprey alloys can be fabricated readily into electronic packages by conventional machining with tungsten‐carbide or polycrystalline diamond (PCD) tools and electro‐discharge machining (EDM). Generally more than one of these conventional machining operations is required in the fabrication process. A new and much faster method has been developed which has been used to produce complete electronic packages from plates of Si–Al alloys in a single machining step. In this novel method, known as thin‐shell electroforming (TSE), an accurate model of the package is produced directly from the drawing in wax using a 3D Systems ThermoJet Modeller. This model is mounted into a frame and it is then plated with a thin copper electroform. The wax model is then melted leaving the electroform attached to the frame. This is backfilled with solder and used as the EDM tool for machining the package from a plate of Si–Al alloy.

This paper describes some recent innovations in design, process and materials in printed circuit laminate technology, which can lead to significant paradigm shifts in the design and application of electronic products. The traditional roles for printed circuit cards and boards have been to provide wiring interconnection capacity, and a robust mechanical structure for the more delicate and costly chips and modules. The advent of surface mount technology eliminated the need for plated‐through holes as anchors for pinned components. The proliferation of light, high performance, multifunction electronic products will lead to light weight, small, low profile printed circuit assemblies. Adding a redistribution layer to the traditional card surface allows flip‐chip‐on‐board and MCM‐L packages as a low‐cost alternative to traditional high density MCM packages, particularly in applications where size, shape and weight are as important as density and performance. Concurrent with the deliberate evolution of traditional printed circuit technology, some important new materials and process innovations have brought about a new generation of laminate capabilities that are particularly important for the future high I/O requirements predicted for the second part of this decade.

Flexible circuits are ideally suited to solving the design demands of next generation electronics. The flexible circuit offers a number of advantages that are unavailable to those using more traditional, rigid type interconnection structures. A number of new applications for flexible circuits have been developed that may well provide a glimpse of what is yet to come in electronic packaging technology. These new applications embrace the whole spectrum of the electronics interconnection world from chip packaging to high density multilayer structures. Reviewed here are some of the more novel uses of the flex circuit for high performance electronic interconnection.

The aim of the present study was to gather and review all the important properties of the Sn–Ag–Cu (SAC) solder alloy. The SAC solder alloy has been proposed as the alternative solder to overcome the environmental concern of lead (Pb) solder. Many researchers have studied the SAC solder alloy and found that the properties such as melting temperature, wettability, microstructure and interfacial, together with mechanical properties, are better for the SAC solder than the tin – lead (SnPb) solders. Meanwhile, addition of various elements and nanoparticles seems to produce enhancement on the prior bulk solder alloy as well. These benefits suggest that the SAC solder alloy could be the next alternative solder for the electronic packaging industry. Although many studies have been conducted for this particular solder alloy, a compilation of all these properties regarding the SAC solder alloy is still not available for a review to say.

Soldering is identified as the metallurgical joining method in electronic packaging industry which uses filler metal, or well known as the solder, with a melting point < 425°C (Yoon et al., 2009; Ervina and Marini, 2012). The SAC solder has been developed by many methods and even alloying it with some elements to enhance its properties (Law et al., 2006; Tsao et al., 2010; Wang et al., 2002; Gain et al., 2011). The development toward miniaturization, meanwhile, requires much smaller solder joints and fine-pitch interconnections for microelectronic packaging in electronic devices which demand better solder joint reliability of SAC solder Although many studies have been done based on the SAC solder, a review based on the important characteristics and the fundamental factor involving the SAC solder is still not sufficient. Henceforth, this paper resolves in stating all its important properties based on the SAC solder including its alloying of elements and nanoparticles addition for further understanding.

Various Pb-free solders have been studied and investigated to overcome the health and environmental concern of the SnPb solder. In terms of the melting temperature, the SAC solder seems to possess a high melting temperature of 227°C than the Pb solder SnPb. Here, the melting temperature of this solder falls within the range of the average reflow temperature in the electronic packaging industry and would not really affect the process of connection. A good amendment here is, this melting temperature can actually be reduced by adding some element such as titanium and zinc. The addition of these elements tends to decrease the melting temperature of the SAC solder alloy to about 3°C. Adding nanoparticles, meanwhile, tend to increase the melting temperature slightly; nonetheless, this increment was not seemed to damage other devices due to the very slight increment and no drastic changes in the solidification temperature. Henceforth, this paper reviews all the properties of the Pb-free SAC solder system by how it is developed from overcoming environmental problem to achieving and sustaining as the viable candidate in the electronic packaging industry. The Pb-free SAC solder can be the alternative to all drawbacks that the traditional SnPb solder possesses and also an upcoming new invention for the future needs. Although many studies have been done in this particular solder, not much information is gathered in a review to give better understanding for SAC solder alloy. In that, this paper reviews and gathers the importance of this SAC solder in the electronic packaging industry and provides information for better knowledge.

This paper resolves in stating of all its important properties based on the SAC solder including its alloying of elements and nanoparticles addition for further understanding.

The mismatch of the thermal expansion coefficients of the materials in multiplayer structure may induce serious stress concentrations in electronic packaging. Experimental evaluation of the thermal stresses and strains in those electronic composites is becoming significantly important for optimizing design and failure prediction of the electronic devices.

Digital image correlation (DIC) technique was utilized to obtain thermal deformation filed of a BGA package. With the help of white light to illuminate the cross section of the BGA package, the gray images were taken from the rough surface of the specimen, that offer a kid of carrier pattern for the DIC processing with statistical resemblance in gray distributions. By using the algorithm of correlation computation, the DIC searched the matching spots in a pair of those images in which the spot displacements were involved in between, to obtain the deformation fields of the package specimen caused by temperature changes.

The results show interesting strain distributions in the assembly. Both the horizontal displacement component and its normal derivative are strongly related to the arrangement of the solder joints in the bonding medium between the die and the ceramic substrate. The strain components in the middle region of the package are larger than those in the side regions where the strain relaxation may exist near the stress‐free boundaries. The shear strain components show special bands of parallel lines with identical amount over the chip‐package to sustain the shearing of the packed structure under thermal loading.

The DIC technique shows to be a useful tool for the thermal strain analysis of the electronic packaging devices. Not only provides it the whole field deformation of the assembly, but also maintains the surface pictures of the package without covering any fringes, which is important to compare the deformation field with the specimen surface to reveal the stain distribution related to the failure prediction of the materials.

This paper aims to demonstrate the improved functionality of additive manufacturing technology provided by combining multiple processes for the fabrication of packaged electronics.

This research is focused on the improvement in resolution of conductor deposition methods through experimentation with build parameters. Material dispensing with two different low temperature curing isotropic conductive adhesive materials was characterised for their application in printing each of three different conductor designs, traces, z-axis connections and fine pitch flip chip interconnects. Once optimised, demonstrator size can be minimised within the limitations of the chosen processes and materials.

The proposed method of printing z-axis through layer connections was successful with pillars 2 mm in height and 550 µm in width produced. Dispensing characterisation also resulted in tracks 134 µm in width and 38 µm in height allowing surface mount assembly of 0603 components and thin-shrink small outline packaged integrated circuits. Small 149-µm flip chip interconnects deposited at a 457-µm pitch have also been used for packaging silicon bare die.

This paper presents an improved multifunctional additive manufacturing method to produce fully packaged multilayer electronic systems. It discusses the development of new 3D printed, through layer z-axis connections and the use of a single electrically conductive adhesive material to produce all conductors. This facilitates the surface mount assembly of components directly onto these conductors before stereolithography is used to fully package multiple layers of circuitry in a photopolymer.