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This paper deals with the problem of input/output-to-state stability (IOSS) of direct-form digital filters, which simultaneously contain external disturbances and two's complement nonlinearity. The nonlinearity under consideration is confined to the sector [–1, 1], which contains saturation, zeroing, two's complement and triangular.

The proposed condition is based on IOSS approach, which is capable of providing a framework for checking and analysing the stability of nonlinear system based on input as well as output information.

A linear matrix inequality (LMI)-based new sufficient criterion for the IOSS of the suggested system is obtained. The obtained criterion is capable of detecting the output-to-state stability (OSS) and asymptotic stability of direct-form digital filters with zero external disturbances. In addition, state-norm estimator for the filter under consideration is constructed by adopting an exponential-decay IOSS criterion. Several examples are provided to illustrate the usefulness of the proposed criteria.

The result of the paper is introduced for the first time, and it is suitable for stability analysis of interfered direct-form digital filter with two's complement overflow using IOSS approach.

The purpose of this paper is to present a criterion for global asymptotic stability of state-space direct-form digital filters employing saturation arithmetic.

An elegant use of induced l _∞ approach (also known as a peak-to-peak approach) is made to develop a criterion for the overflow stability of state-space direct-form digital filters.

The criterion not only guarantees asymptotic stability but also reduces the effect of external interference. The presented method yields better interference attenuation level as compared to a recently reported method. Numerical examples are given to illustrate the effectiveness of the proposed method.

Digital filters are important dynamical systems in signal processing which are used for the processing of discrete signals. During the implementation of higher-order digital filter in hardware or software, introduction of external interference is unavoidable. Therefore, stability analysis of digital filters in the presence of external interference is of much practical importance.

The main result of the paper is reported for the first time and it is useful to establish the asymptotic stability of digital filters in the presence of external disturbances.

The purpose of this paper is to develop a new criterion for the exponential stability and

_∞ performance of state-space digital filters under the influence of any combination of quantization/overflow nonlinearities.

The proposed criterion uses the

_∞ approach that is suitable for the design of discrete system in the presence of external disturbance. Analysis and synthesis in an

_∞ setting is advantageous as it proposes effective disturbance attenuation, less sensitivity to uncertainties and many practical applications.

The criterion not only guarantees exponential stability but also reduces the effect of external interference. A numerical example demonstrating the effectiveness of the proposed method is given.

The main result of the paper is reported for the first time and it is useful to ensure the stability of digital filters in the presence of external disturbance and any combination of quantization/overflow nonlinearities.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

The purpose of this paper is to establish a criterion for the global asymptotic stability of fixed-point state–space digital filters using saturation overflow arithmetic.

The method of stability analysis used in this paper is the second method of Lyapunov. The approach in this paper makes use of a precise upper bound of the state vector of the system and a novel passivity property associated with the saturation nonlinearities.

The presented criterion leads to an enhanced stability region in the parameter-space as compared to several existing criteria.

When dealing with the design of fixed-point state–space digital filters, it is desirable to have a criterion for selecting the filter coefficients so that the designed filter becomes free of overflow oscillations. The criterion presented in this paper provides enhanced saturation overflow stability region and therefore facilitates the designer greater flexibility in selecting filter parameters for overflow oscillation-free realization of digital filters.

The approach uses the structural properties of the saturation nonlinearities in a greater detail. The exploitation of upper bound of the system state vector together with a new passivity property of saturation nonlinearities is a unique feature of the present approach. The presented approach may lead to results not covered by several existing approaches.

This paper deals with the application of a Tabu Search (TS) metaheuristic to the design of digital filters, with coefficient values expressed as the sum of power of two. The performances of the algorithm are heavily affected by the choice of its parameters, which in turn are related to different implemented strategies. The tuning of these parameters has been performed after many tests. The results of the proposed technique are compared to those obtained by simply rounding the optimal values of coefficients obtained by means of Remetz algorithm, and to those obtained using a simulated annealing algorithm.

The purpose of this paper is to find the best way to obtain the Sagnac phase shift in the output signal of open loop interferometric fiber optic gyroscopes (IFOGs). Also, the utilized digital filtering based on FIR kaiser window for implementing the digital signal processing part is evaluated.

The approach is based on implementing four kaiser FIR filters, the coefficients of which have been obtained from SPtool. They were simulated with SPtool in the Matlab 7.1.

The results show that the chosen computational method has reliable accuracy. On the other hand, it could require low‐computational effort, and it is a simple way which is important for the signal processors.

The limitation in this paper is that the designed filters have high order and they require much time; therefore, a high‐speed device is needed. For solving this problem, it is proposed to perform some estimation by experiments.

IFOGs are used in aircraft, missiles, and new civil fields such as automobile navigation, antenna stabilization, crane control, unmanned vehicle control, wind, and renewable energy platform stabilization.

There is no other paper which has explained mathematics of IFOG implementation in the signal processing part as completely as is done here.

Traditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.

Rather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.

An ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.

A software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.

RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.

In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.

The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.