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1 – 7 of 7B.N. Mohan Kumar and H.G. Rangaraju
Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed…
Abstract
Purpose
Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.
Design/methodology/approach
The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.
Findings
The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.
Originality/value
The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.
Details
Keywords
C. Srinivasa Murthy and K. Sridevi
In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter…
Abstract
Purpose
In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.
Design/methodology/approach
The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.
Findings
Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.
Originality/value
The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.
Details
Keywords
Britto Pari J., Mariammal K. and Vaithiyanathan D.
Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters…
Abstract
Purpose
Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.
Design/methodology/approach
RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.
Findings
In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.
Originality/value
The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.
Details
Keywords
B.N. Mohan Kumar and H.G. Rangaraju
Finite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the…
Abstract
Purpose
Finite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs.
Design/methodology/approach
To overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices.
Findings
The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.
Originality/value
The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.
Details
Keywords
Abstract
Purpose
Traditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.
Design/methodology/approach
Rather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.
Findings
An ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.
Originality/value
A software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.
Details
Keywords
A. Pasumponpandian, Robert Bestak, Klimis Ntalianis and Ram Palanisamy
Fernando Menchini, Paschoal Tadeu Russo, Tiago Nascimento Borges Slavov and Rodrigo Paiva Souza
The purpose of this paper is to understand the association between the capacity to use enterprise architecture tools and the effectiveness of business model digitalization in…
Abstract
Purpose
The purpose of this paper is to understand the association between the capacity to use enterprise architecture tools and the effectiveness of business model digitalization in companies.
Design/methodology/approach
The authors used two research strategies – survey and focus group – to analyze the relationship between maturity in using enterprise architecture (EA) and digital maturity, under the perspective of sociomateriality.
Findings
The use of EA is not a strategic competence that contributes to building sustainable competitive advantage, in the process of business model digitalization. On the other hand, top management’s determination and clarity, expressed by its sponsorship to communicating the strategy, contribute to the integration, engagement and adaptability of those involved and are responsible for higher maturity in the digitalization of business models.
Research limitations/implications
The statistical treatment used does not allow understanding the causality between the variables.
Practical implications
It provides executives with important elements for clarifying and operationalizing digital business models.
Originality/value
The study operationalizes a theoretical and measurement model, through a strategy that used simultaneously a survey and a focus group, which allowed to know associations between technological capacities and maturity in digital business models.
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