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In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.

RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.

In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.

The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

The purpose of this paper is to propose the basis for the unification of unmanned aerial vehicle (UAV) group control protocols for the fast deployment of communication network on territories unsuitable for stationary nodes placement.

The paper proposes the application of active data (AD) conception in which the data exist in a form of executable code allowing data packets to control its own propagation through network. The implementation is illustrated for some scenarios of UAV data communication network deployment, i.e., transmission of the AD using navigation functions and dynamic reconfiguration of the nodes.

The conception of AD expands the range of possible UAV group operations due to on-the-fly adaptation abilities to changes in existing or forthcoming group behavior protocols. This allows the real-time change of data transmission formats, frequency ranges, modulation types, radio network topologies which, in turn, provides the ability to dynamically form the special data transmission networks from a general purpose device temporarily reconfiguring them for data transmission task between transmitter and receiver beyond radio visibility range.

The paper includes use cases for some situation of UAV data communication network deployment.

The paper aims to expand the UAV group control principles by implementing by rapid adaptation to changes in existing or forthcoming group behavior protocols.

The purpose of this paper is to present an approach to employ evolvable hardware concepts, to effectively construct flapping‐wing mechanism controllers for micro robots, with the evolved dynamically complex controllers embedded in a, physically realizable, micro‐scale reconfigurable substrate.

In this paper, a continuous time recurrent neural network (CTRNN)‐evolvable hardware (a neuromorphic variant of evolvable hardware) framework and methodologies are employed in the process of designing the evolution experiments. CTRNN is selected as the neuromorphic reconfigurable substrate with most efficient Minipop Evolutionary Algorithm, configured to drive the evolution process. The uniqueness of the reconfigurable CTRNN substrate preferred for this study is perceived from its universal dynamics approximation capabilities and prospective to realize the same in small area and low power chips, the properties which are very much a basic requirement for flapping‐wing based micro robot control. A simulated micro mechanical flapping insect model is employed to conduct the feasibility study of evolving neuromorphic controllers using the above‐mentioned methodology.

It has been demonstrated that the presented neuromorphic evolvable hardware approach can be effectively used to evolve controllers, to produce various flight dynamics like cruising, steering, and altitude gain in a simulated micro mechanical insect. Moreover, an appropriate feasibility is presented, to realize the evolved controllers in small area and lower power chips, with available fabrication techniques and as well as utilizing the complex dynamics nature of CTRNNs to encompass various controls ability in a architecturally static hardware circuit, which are more pertinent to meet the constraints of micro robot construction and control.

The proposed neuromorphic evolvable hardware approach along with its modules intact (CTRNNs and Minipop) can provide a general mechanism to construct/evolve dynamically complex and optimal controllers for flapping‐wing mechanism based micro robots for various environments with least human intervention. Further, the evolved neuromorphic controllers in simulation study can be successfully transferred to its hardware counterpart without sacrificing its anticipated functionality and realized within a predictable area and power ranges.

The purpose of this paper is to present an organized review of existing research on reconfigurable manufacturing system (RMS). The paper considers majority of the prominent research articles in the domain of RMS published ever since RMS was envisaged in 1997.

The paper systematically reviews, classifies and analyses the published literature on postulations and design of RMSs. The general observations from the literature and research gaps recognized thereon are highlighted at the end of each section/sub-section.

The paper reveals important aspects related to RMS research since its inception. It also recognizes the areas of RMS research requiring more focus. The study also highlights open issues and future directions for further research.

The literature in the domain of RMS has so far been narrow. This paper reviews the prominent research in this field and presents an overview of its conceptual developments and various mathematical models for the RMS design and its optimization so far developed by the researchers. Further, manufacturing advancements and future directions have also been proposed for the efficient execution of RMS paradigm in manufacturing industries.

The paper provides an organized listing of published research work in the field of RMS. This work will provide an insight to the researchers, practitioners and others related directly or indirectly to this field to develop and understand better strategies for supervising and controlling the smooth implementation of RMS.

With the rapid development in wired and wireless networks, the demand for network security system is rising rapidly due to more and more new applications introduced. The main factors that rate the encryption algorithms are its ability to secure and protect data against attacks, its speed and efficiency. In this paper, a reconfigurable network security design using multi-mode data encryption standard (DES) algorithm has been implemented with low complexity and low cost, which will also reduce the speed. The paper aims to discuss these issues.

The design can be easily reconfigured to 3DES (triple DES) which is more secure and more powerful in encryption and decryption, as one of the trick in designing 3DES is to reuse three instances of DES. The design can be used for wired and wireless network applications, and it has been described using VHDL and implemented in a reconfigurable Programmable System-on-Chip (PSoC). The hardware implementation has targeted Xilinx Spartan XC3S700-AN FPGA device.

The main idea of reducing the complexity for the hardware implementation is by optimizing the number of logic gates and LUTs of the design. The number of logic gates can be decreased by changing the way of writing the VHDL code and by optimizing the size of the chip.

The design has been tested in simulation and hardware levels, and the simulation results and performance are discussed.

The purpose of this paper is to conduct a systematic bibliometric analysis of reconfigurable manufacturing system (RMS) articles using VOSviewer to identify their research themes and future research trends and investigate their interconnectivity. This paper also aims to identify prominent authors, publishers, organizations, countries and their collaborations in the RMS domain.

In this study, the Scopus database is used to retrieve 454 RMS articles published between 1988 and 2020. These articles are then investigated using VOSviewer to determine their interconnectedness, clusters and citations, as well as to generate a map based on text data. The network visualization diagrams and clusters obtained for documents, authors, sources, organizations and countries are explored to determine the current state and future trends in RMS research.

A bibliometric analysis of selected articles is performed, and current research hotspots in this domain are identified. This work also investigates the current status and future research trends in this domain. The work presented also identifies top researchers, journals, countries and documents in RMS.

This paper can provide academics, researchers and practitioners with additional research insights. At the same time, the research trends identified here can help to direct research and benefit researchers.

The study is the first attempt to review selected documents in the RMS domain using bibliometric analysis tools, and it presents a method for collecting articles, organizing them and analyzing the data.

The purpose of this paper was the design, development, and test of a flexible and reconfigurable experimental setup for the automatic manipulation of microcomponents, enhanced by an accurately developed vision-based control.

To achieve a flexible and reconfigurable system, an experimental setup based on 4 degrees of freedom robot and a two-camera vision system was designed. Vision-based strategies were adopted to suitably support the motion system in easily performing precise manipulation operations. A portable and flexible program, incorporating the machine vision module and the control module of the task operation, was developed. Non-conventional calibration strategies were also conceived for the complete calibration of the work-cell. The developed setup was tested and exploited in the execution of repetitive tests of the grasping and releasing of microcomponents, testing also different grasping and releasing strategies.

The system showed its ability in automatically manipulating microcomponents with two different types of vacuum grippers. The performed tests evaluated the success and precision of the part grasping and release, which is a crucial aspect of micromanipulation. The results confirm reliability in grasping and that the release is precluded by adhesive effects. Thus, different strategies were adopted to improve the efficiency in the release of stuck components without negatively affecting the accuracy nor the repeatability of the positioning.

This work provided a flexible and reconfigurable architecture devoted to the automatic manipulation of microcomponents, methodologies for the characterization of different vacuum microgrippers, and quantitative information about their performance, to date missing in literature.

The aims of this article are to introduce a modularization framework and a method for the formation of modules.

A methodological framework is presented to guide designers and engineers in the formation and selection of suitable modules in developing customized products. Detailed explanations of the framework are presented theoretically. This framework interacts with different product development participants such as resources, customers' preferences, design architecture for planning, and scheduling a custom‐built product. A new method is proposed with a case example to facilitate the formation of modules.

This paper investigates the potential of the modularization framework, usable for prioritizing the components dependencies and creating required number of modules. It also explains the overall concept, usability and rules/methods for the module formation applied to product design, to allow a greater degree of freedom for the designer, and the opportunity to reduce development time and increase customer satisfaction. A method, based on the rules for modularity concept is proposed within the scope of this paper.

The framework and the method of modularization as illustrated in this article are based on a theoretical hypothesis. Both the approaches require implementing in a real industrial environment in order to generalize their effectiveness, applicability and consistency in the manufacturing arena.

Since product architecture is an important element in determining the value and flexibility of the product development process, the relationship pattern between the architecture and productivity is therefore worthy of careful investigation. The aims of modular framework and rules for modularity are to incorporate design variables and dependency structure with a view to enhancing product development lead time and will contribute to the exploitation of overall bottlenecks of manufacturing systems.

The implementation framework for modular product architecture seems unique as its potential value could be applied in the industrial environment for production flexibility and reducing bottlenecks. Along with the framework, the presented modularity rule or method will contribute to business architecture with a view to providing more reliable operation, easier maintenance and faster product development time.