Search results

Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.

RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.

In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.

The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

This paper aims to concentrate on an efficient finite impulse response (FIR) filter architecture in combination with the differential evolution ant colony algorithm (DE-ACO). For the design of FIR filter, the evolutionary algorithm (EA) is found to be very efficient because of its non-conventional, nonlinear, multi-modal and non-differentiable nature. While focusing with frequency domain specifications, most of the EA techniques described with the existing systems diverge from the power related matters.

The FIR filters are extensively used for many low power, low complexities, less area and high speed digital signal processing applications. In the existing systems, various FIR filters have been proposed to focus on the above criterion.

In the proposed method, a novel DE-ACO is used to design the FIR filter. It focuses on satisfying the economic power utilization and also the specifications in the frequency domain.

The proposed DE-ACO gives outstanding performance with a strong ability to find optimal solution, and it has got quick convergence speed. The proposed method also uses the Software integrated synthesis environment (ISE) project navigator (p.28xd) for the simulation of FIR filter based on DE-ACO techniques.

Finite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs.

To overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices.

The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter.

Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC.

The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption.

The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.

With the growing system‐on‐a‐chip (SOC) design complexity, SOC verification has become a major congestion. In this context, efficient and reliable verification environment is requested for SOC design before it is committed to production. The purpose of this paper is to judge whether the hardware and or software (HW/SW) co‐verification environment can handle SOC verification and provide the necessary performance in terms of co‐verification speed and throughput, power and resource consumption, timing analysis, etc.

A finite‐impulse‐response filter is utilized as a device‐under‐test to compare pure SW simulation, Modelsim simulator in this case, and HW/SW co‐verification approaches to decide on whether the HW/SW co‐verification environment can do work or not. In addition, the performance of the HW/SW co‐verification environment is estimated based on specifications such as co‐verification speed and throughput, power and resource consumption, and timing analysis.

From experiment results, conclusions can be drawn that the more complicated SOC is, the greater the potential speedup of the co‐verification approach over SW simulation is. However, the communication between SW and HW in HW/SW co‐verification system is a major congestion, which may offset the acceleration achieved by moving large computation from the SW to the HW side.

Performance estimation for the HW/SW co‐verification environment has been conducted in terms of co‐verification speed and throughput, power and resource consumption, timing analysis, etc.

The purpose of this paper is to present an approach for the decentralization of swarm intelligence algorithms that run on computing systems with autonomous components that are connected by a network. The approach is applied to a particle swarm optimization (PSO) algorithm with multiple sub‐swarms. PSO is a nature inspired metaheuristic where a swarm of particles searches for an optimum of a function. A multiple sub‐swarms PSO can be used for example in applications where more than one optimum has to be found.

In the studied scenario the particles of the PSO algorithm correspond to data packets that are sent through the network of the computing system. Each data packet contains among other information the position of the corresponding particle in the search space and its sub‐swarm number. In the proposed decentralized PSO algorithm the application specific tasks, i.e. the function evaluations, are done by the autonomous components of the system. The more general tasks, like the dynamic clustering of data packets, are done by the routers of the network.

Simulation experiments show that the decentralized PSO algorithm can successfully find a set of minimum values for the used test functions. It was also shown that the PSO algorithm works well for different type of networks, like scale‐free network and ring like networks.

The proposed decentralization approach is interesting for the design of optimization algorithms that can run on computing systems that use principles of self‐organization and have no central control.

Lean Six Sigma 4.0 has brought about a paradigm shift in customization, automation, value creation and digitalization to achieve excellence in human factors, operations and sustainable development. Despite its potential, LSS 4.0 is still in its nascent stage, with researchers striving to identify the key and relevant components of LSS in relation to Industry 4.0. The present study aims to address this knowledge gap through a literature review and subsequently provide a conceptual framework for LSS within the context of digital transformation.

In this study, the authors have conducted a thorough review of reputable articles published between 2011 and 2022, focusing on the integration of Lean Six Sigma (LSS) and Industry 4.0 (I4.0). By using appropriate keywords, the authors identified around 85 relevant articles. The main objective of this integrative literature review was to analyze and extract valuable knowledge from the existing literature on LSS and I4.0. Based on the authors’ findings, a conceptual framework was developed.

The review revealed the motivators, building blocks, tools and challenges of LSS 4.0. The conceptual framework delves into the key aspects of LSS 4.0, focusing on the dimensions of people, process and technology, as well as their subdimensions. These subdimensions serve as the building blocks for developing LSS 4.0 capabilities. The proposed framework visually represents the conceptualization and the relationships among its components.

Only a few conceptual approaches to LSS are developed that include the concepts, new roles and elements of I4.0. As a result, this research investigates the gap in current LSS models preceding I4.0 and develops a conceptual framework to provide a novel and comprehensive summary of the new concepts and components driving nascent and current LSS practices in the digital era.

This study offers practical guidance for implementing LSS in the context of I4.0, emphasizing digital transformation. The findings highlight motivators, building blocks, tools, challenges and spread of LSS 4.0 practices, and present a conceptual framework of LSS 4.0. These insights can help organizations enhance their LSS capabilities and achieve excellence in human factors, operations and sustainable development.

This study aims to make a significant contribution to the model-building efforts of researchers focusing on LSS 4.0. By offering practical guidance, the points discussed in this study help enhance the implementation efforts of practitioners and organizations in the context of I4.0, with a specific focus on digital transformation. The guidance provided takes into account the perspectives of people, processes and technology, providing valuable insights for successful integration.