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Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

The objective of this paper is to investigate the efficiency of hybrid solution methods when incorporated into large‐scale optimization problems solved by evolution strategies (ESs) and to demonstrate their influence on the overall performance of these optimization algorithms. ESs imitate biological evolution and combine the concept of artificial survival of the fittest with evolutionary operators to form a robust search mechanism. In this paper modified multi‐membered evolution strategies with discrete variables are adopted. Two solution methods are implemented based on the preconditioned conjugate gradient (PCG) algorithm. The first method is a PCG algorithm with a preconditioner resulted from a complete Cholesky factorization, and the second is a PCG algorithm in which a truncated Neumann series expansion is used as a preconditioner. The numerical tests presented demonstrate the computational advantages of the proposed methods, which become more pronounced in large‐scale optimization problems and in a parallel computing environment.

The purpose of this paper is to reduce the calculation burden and speed up the estimation process of Allan variance method while ensuring the exactness of the analysis results.

A series of six‐hour static tests have been implemented at room temperature, and the static measurements have been collected from MEMS IMU. In order to characterize the various types of random noise terms for the IMU, the basic definition and main procedure of the Allan variance method are investigated. Unlike the normal Allan variance method, which has the shortcomings of processing large data sets and requiring long computation time, a modified Allan variance method is proposed based on the features of data distribution in the log‐log plot of the Allan standard deviation versus the averaging time.

Experiment results demonstrate that the modified Allan variance method can effectively estimate the noise coefficients for MEMS IMU, with controllable computation time and acceptable estimation accuracy.

This paper proposes a time‐controllable Allan variance method which can quickly and accurately identify different noise terms imposed by the stochastic fluctuations.

The purpose of this paper is to propose a lossy/lossless binary textual image compression method based on an improved pattern matching (PM) technique.

In the Farsi/Arabic script, contrary to the printed Latin script, letters usually attach together and produce various patterns. Hence, some patterns are fully or partially subsets of some others. Two new ideas are proposed here. First, the number of library prototypes is reduced by detecting and then removing the fully or partially similar prototypes. Second, a new effective pattern encoding scheme is proposed for all types of patterns including text and graphics. The new encoding scheme has two operation modes of chain coding and soft PM, depending on the ratio of the pattern area to its chain code effective length. In order to encode the number sequences, the authors have modified the multi‐symbol QM‐coder. The proposed method has three levels for the lossy compression. Each level, in its turn, further increases the compression ratio. The first level includes applying some processing in the chain code domain such as omission of small patterns and holes, omission of inner holes of characters, and smoothing the boundaries of the patterns. The second level includes the selective pixel reversal technique, and the third level includes using the proposed method of prioritizing the residual patterns for encoding, with respect to their degree of compactness.

Experimental results show that the compression performance of the proposed method is considerably better than that of the best existing binary textual image compression methods as high as 1.6‐3 times in the lossy case and 1.3‐2.4 times in the lossless case at 300 dpi. The maximum compression ratios are achieved for Farsi and Arabic textual images.

Only the binary printed typeset textual images are considered.

The proposed method has a high‐compression ratio for archiving and storage applications.

To the authors' best knowledge, the existing textual image compression methods or standards have not so far exploited the property of full or partial similarity of prototypes for increasing the compression ratio for any scripts. Also, the idea of combining the boundary description methods with the run‐length and arithmetic coding techniques has not so far been used.

Investigates the efficiency of hybrid solution methods when incorporated into large‐scale topology and shape optimization problems and to demonstrate their influence on the overall performance of the optimization algorithms. Implements three innovative solution methods based on the preconditioned conjugate gradient (PCG) and Lanczos algorithms. The first method is a PCG algorithm with a preconditioner resulted from a complete or an incomplete Cholesky factorization, the second is a PCG algorithm in which a truncated Neumann series expansion is used as preconditioner, and the third is a preconditioned Lanczos algorithm properly modified to treat multiple right‐hand sides. The numerical tests presented demonstrate the computational advantages of the proposed methods which become more pronounced in large‐scale and/or computationally intensive optimization problems.

The chapter offers complete details of the latest SGL version particularly suitable for dealing with large security systems and emerging crisis situations. It describes main types of constants representing information, physical matter or both and five very different and specific types of variables operating in fully distributed spaces and even being mobile themselves when serving spreading algorithms. Also given full repertoire of the language operations, called rules, which can be arbitrarily nested and carry different navigation, creation, processing, assignment, control, verification, context, exchange, transference, echoing, timing and other loads. The rules equally operate with local and remote values, process both, matter and distributed networked knowledge, and can express active graph-based patterns navigating, matching, conquering and changing distributed environments. Elementary programming examples in SGL are also provided.

The chapter describes the basics of developed high-level spatial grasp technology (SGT) and its spatial grasp language (SGL) allowing us to create and manage very large distributed systems in physical, virtual and executive domains in a highly parallel manner and without any centralized resources. Main features of SGT with its self-evolving and self-spreading spatial intelligence, recursive nature of SGL and organization of its networked interpreter will be briefed. Numerous interpreter copies can be installed worldwide and integrated with other systems or operate autonomously and collectively in critical situations. Relation of SGT, with capability of holistic solutions in distributed systems, to the gestalt psychology and theory, showing unique qualities of human mind and brain to directly grasp the whole of different phenomena, will be explained too, with SGT serving as an attempt to implement the notion of gestalt for distributed applications.

Very large-scale integration (VLSI) digital signal processing became very popular and is predominantly used in several emerging applications. The optimal design of multirate filter with improvement in performance parameters such as less area, high speed and less power is the challenging task in most of the signal processing applications. This study aims to propose several effective multirate filter structures to accomplish sampling rate conversion.

The multirate filter structures considered in this work are polyphase filter and coefficient symmetry-based finite impulse response filter. The symmetry scheme particularly brings down the complexity to significant extent. To bring improvement in speed, delay registers are inserted at appropriate path with the help of pipelining and retiming scheme.

In this paper, the three tasks have been considered. First, the polyphase coefficient symmetry and modified polyphase (MP) structure is designed. Second, the pipelining is applied to the polyphase structure and the obtained results are compared with the polyphase structure. In third, retiming is applied to the polyphase structure and the performance comparison is carried out. The structures are realized for various orders, and the comparative analysis is carried out with the filter order N = 12, 30, 42, 8, 11 and 24 and the results are stated. The performance of all the accomplished structures is analyzed using Altera Quartus with the family cyclone II, device EP2C70F672C6. The results show that the multirate filter using pipelining and retiming offers better performance when examining with the conventional structures. Retimed and pipelined MP structure achieves a speed enhancement of about 33.81% when examining with the conventional polyphase (CP) structure with retiming and pipelining for N = 24 and M = 5. Likewise, the 2/3 structure of pipelined coefficient symmetry approach offers area reduction of about 54.76% over 2/3 structure of pipelined polyphase approach for N = 30 with little reduction in power. The fine grain pipelined and retimed MP structure with N = 11 and M = 3 avails critical path delay reduction of about 28.15% when examining with the corresponding fine grain pipelined and retimed CP structure.

The proposed distinct structures offer better alternative to conventional structures because of the symmetric coefficients, performance enhancement using pipelining and retiming based rate conversion structures. The suggested structures can be used for achieving different rates in software radios.

The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications.

The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.