Search results

A real-time production scheduling method for semiconductor back-end manufacturing process becomes increasingly important in industry 4.0. Semiconductor back-end manufacturing process is always accompanied by order splitting and merging; besides, in each stage of the process, there are always multiple machine groups that have different production capabilities and capacities. This paper studies a multi-agent based scheduling architecture for the radio frequency identification (RFID)-enabled semiconductor back-end shopfloor, which integrates not only manufacturing resources but also human factors.

The architecture includes a task management (TM) agent, a staff instruction (SI) agent, a task scheduling (TS) agent, an information management center (IMC), machine group (MG) agent and a production monitoring (PM) agent. Then, based on the architecture, the authors developed a scheduling method consisting of capability & capacity planning and machine configuration modules in the TS agent.

The authors used greedy policy to assign each order to the appropriate machine groups based on the real-time utilization ration of each MG in the capability & capacity (C&C) planning module, and used a partial swarm optimization (PSO) algorithm to schedule each splitting job to the identified machine based on the C&C planning results. At last, we conducted a case study to demonstrate the proposed multi-agent based real-time production scheduling models and methods.

This paper proposes a multi-agent based real-time scheduling framework for semiconductor back-end industry. A C&C planning and a machine configuration algorithm are developed, respectively. The paper provides a feasible solution for semiconductor back-end manufacturing process to realize real-time scheduling.

This study aims to understand how Brazilian design houses (DHs) use open innovation in joint development projects for integrated circuits.

As a research strategy, qualitative research using multiple case studies was made. As sources of evidence, semi-structured interviews were conducted with three DHs of Programa integrated circuit [circuito integrado(CI)]-Brasil and with four specialists in the field, as well as analysis of documents. The data were analyzed through content analysis.

The results showed the DHs use sources of external knowledge in their innovation process, to assist the development of new products, to access new knowledge and skills, to attract financial resources and to be competitive in the market of high technology.

The study has important implications on the semiconductor industry in Brazil, as the industry is considered strategic for the competitiveness of final goods sector. The importance of encouraging the development of partnerships in the sector, the possibility of using informal agreements to mediate the collaboration between DHs and external agents, and the improvement and long-term continuity of public policies to support the industry are among the implications. In addition to suggestions for new business approaches to assist the strengthening of this segment.

In recent years, both academics and institutions have acknowledged the crucial role multinational enterprises (MNEs) can play in addressing the sustainability challenges, as formalized by the sustainable development goals (SDGs). Nevertheless, because of their extensiveness and their design as country-level targets, SDGs have proven challenging to operationalize at a firm level. This problem opens new and relevant avenues for research in international business (IB). This chapter attempts to frame the topic of extended value chain sustainability in the IB literature. In particular, it addresses a specific topic, that is, how sustainability and resilience-building practices interact in global value chains (GVCs). To do so, the present study develops the case of STMicroelectronics (ST), one of the biggest semiconductor companies worldwide.

This paper aims at exploring the interactions between Japan's export curbs against Korea, dubbed as “weaponized interdependence,” and Korea's decoupling from Japan' phenomenon in response. Thereby, it sheds light on the characteristics of the semiconductor industry, where the two economies' effective division of labor takes place. In addition, it attempts to typology the “decoupling from Japan” into two types. Furthermore, it deals with the political-economic implications of bilateral trade disputes and projects in the future.

This paper segregates the economic concept of “decoupling” into “decoupling from Japan” and “decoupling from Japanese firms” to better analyze the related phenomenon that occurred in Korea in response to the Japanese government's export restrictions in 2019. Along with it, the paper attempts to observe the trade dispute between Korea-Japan from a political-economic point of view.

The main findings are: First, Korea's decoupling from Japan' does not necessarily mean “decoupling from Japanese firms”. When Korean firms had to decouple from Japan due to non-economic factors, some has circumvented the decoupling to maintain economic ties with Japanese firms in the market, stemming from long-term transaction relationships in the semiconductor industry. Second, the two countries were confronted in a modest manner, even though they seemed to be fighting like a fierce tit-for-tat chicken game as those economies are interdependent with one another. Hence, both put effort to avoid sober damages or disruptive results on two economies and the global semiconductor supply chain.

The originality of this paper is to typologize the characteristics of “decoupling from Japan” in Korea by segregating it into two types of decoupling. On the other hand, other previous studies appeal to focus on the decoupling phenomenon per se and are interested in its potential for success.

In this paper, we evaluated the impact of the US “Chip Act” on the participation of the Chinese electronics industry in the global value chain based on the dynamic CGE model. This is a meaningful attempt to use the GTAP-VA model to analyze the electronics industry in China.

We employ a Dynamic GTAP-VA Model to quantitatively evaluate the economic repercussions of the “Chip Act” on the Chinese electronic industries' GVC participation from 2023 to 2040.

The findings depict a discernible contraction in China’s electronic sector by 2040, marked by a −2.95% change in output, a −3.50% alteration in exports and a 0.45% increment in imports. Concurrently, the U.S., EU and certain Asian economies exhibit expansions within the electronic sector, indicating a GVC realignment. The “Chip Act” implementation precipitates a significant divergence in GVC participation across different countries and industries, notably impacting the electronics sector.

Through a meticulous temporal analysis, this manuscript unveils the nuanced economic shifts within the GVC, substantially bridging the empirical void in existing literature. This narrative accentuates the profound implications of policy regulations on global trade dynamics, contributing to the discourse on international economic policy and industry evolution.

We evaluated the impact of the US “Chip Act” on the participation of the Chinese electronics industry in the global value chain based on the dynamic CGE model. This is a meaningful attempt to use the GTAP-VA model to analyze the electronics industry in China.

The interaction between policy regulations and global value chain (GVC) dynamics is pivotal in understanding the contemporary global trade framework, especially within technology-driven sectors. The US “Chips Act” represents a significant regulatory milestone with potential ramifications on the Chinese electronic industries' engagement in the GVC.

The significance of this paper is that it quantifies for the first time the impact of the US Chip Act on the GVC participation index of East Asian countries in the context of US-China decoupling. With careful consideration of strategic aspects, this paper substantially fills the empirical gap in the existing literature by presenting subtle economic changes within GVCs, highlighting the profound implications of policy regulation on global trade dynamics.

China has been the most important economic partner to Korea since the resurrection of their diplomatic relationship and economic interaction. It has been suggested that China simultaneously presents challenges and opportunities to the Korean economy. This paper investigates changes in trade specialization patterns and comparative advantage of Korea and China, and analyzes the effect of market expansion of Chinese industries on market shares of Korean industries. It is found that since the early 1990s, the industries that lost market share as China’s share increased include those in which Korea has maintained a comparative advantage or improved the level of disadvantage, such as IT equipment and other transport equipments. Considering growth of trade flows and emergence of China, it is critical for Korea to actively participate in international production chains, create competitive edges and extend complementary relationship with trading partners.

In the aftermath of the COVID-19 pandemic, supply chains have become important policy tools to ensure the security and resilience of regional trading blocs of major economies. The US government’s focus on supply chains for selected strategic industries and the EU Commission’s renewed efforts to strengthen its supply chains using ‘sustainability standards’ coincides with the global trend in the shift towards digital and low-carbon economies. Furthermore, the rising tensions between the US and China, with no signs of reconciliation over key issues of contention, have emphasized the need for more credibility and trust in global supply chains. However, such policies also have the potential to serve as new barriers to participation in supply chains by less-developed economies which are not yet prepared to meet the high-level sustainability criteria which aim for higher protection of the environment and labor rights. There also seems to be an apparent shift in paradigm supporting the interventionist role of government that emphasize the need for more discretion for policy objectives that pursue societal and democratic values, not to mention national security interests. The current rules of international trade, however, do not sufficiently address these new issues and need to be realigned in order to meet the new demands. The current ‘rules of the game’ need to be reinforced in order to accommodate the rising need of countries for increased consideration of issues of sustainability and competitiveness.

The purpose of this paper is to develop and test the thermal interface materials (TIM) for application in assembly of semiconductor chips to package. Good adhesion properties (>5 MPa shear strength) and low thermal interface resistance (better than for SAC solders) are the goal of this research.

Mechanical and thermal properties of TIM joints between gold plated contacts of chip and substrate were investigated. Sintering technique based on Ag pastes was applied for purpose of this study. Performance properties were assessed by shear force tests and thermal measurements. Scanning electron microscopy was used for microstructural observations of cross-section of formed joints.

It was concluded that the best properties are achieved for pastes containing spherical Ag particles of dozens of micrometer size with flake shaped Ag particles of few micrometers size. Sintering temperature at 230°C and application of 1 MPa force on the chip during sintering gave the higher adhesion and the lowest thermal interface resistance.

The new material based on Ag paste containing mixtures of Ag particles of different size (form nanometer to dozens of microns) and shape (spherical, flake) suspended in resin was proposed. Joints prepared using sintering technique and Ag pastes at 230°C with applied pressure shows better mechanical and thermal than other TIM materials such as thermal grease, thermal gel or thermally conductive adhesive. Those material could enable electronic device operation at temperatures above 200°C, currently unavailable for Si-based power electronics.

The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu₃Sn layer which locate between the intermetallic Cu₆Sn₅ and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu₃Sn and Cu₆Sn₅ do affected seriously by heat, but Ni₃Sn₄ is not affected by heat or moisture.

The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology.

The Cu₆Sn₅ intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu₃Sn IMC. Cu₆Sn₅ IMC will convert to Cu₃Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu₃Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni₃Sn₄ IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni₃Sn₄ IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell.

The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design.

This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology.

The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.