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The purpose of this paper is to fabricate a new Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration.

The Cu-Sn-Ni-Cu interconnection microstructure is fabricated by a three-mask photolithography process with different electroplating processes. This microstructure consists of pads and conductive lines as the bottom layer, Cu-Sn-Ni-Cu pillars with the diameter of 10-40 μm as the middle layer and Cu conductive lines as the top layer. A lift-off process is adopted for the bottom layer. The Cu-Sn-Ni-Cu pillars are fabricated by photolithography with sequential electroplating processes. To fabricate the top layer, a sputtered Cu layer is introduced to prevent the middle-layer photoresist from being developed. With the final Cu electroplating processes, the Cu-Sn-Ni-Cu interconnection microstructure is successfully achieved.

The surface morphology of Cu-Sn pillars consists of densely packed clusters which are formed by an ordered arrangement of tetragonal Sn grains. The diffusion of Cu atoms into the Sn phases is observed at the Cu/Sn interface. Furthermore, the obtained Cu-Sn-Ni-Cu pillars have a flat surface with an average roughness of 13.9 nm. In addition, the introduction of Ni layer between the Sn and the top Cu layers in the Cu-Sn-Ni-Cu pillars can mitigate the diffusion of Cu atoms into Sn phases. The process is verified by checking the electrical performance using four-point probe measurements.

The method described in this paper which combined a three-mask photolithography process with sequential Cu, Sn, Ni and Cu electroplating processes provides a new way to fabricate the interconnection microstructure for future electromigration studies.

The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering.

In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method.

The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation.

This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process.

The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu₃Sn layer which locate between the intermetallic Cu₆Sn₅ and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu₃Sn and Cu₆Sn₅ do affected seriously by heat, but Ni₃Sn₄ is not affected by heat or moisture.

The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology.

The Cu₆Sn₅ intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu₃Sn IMC. Cu₆Sn₅ IMC will convert to Cu₃Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu₃Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni₃Sn₄ IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni₃Sn₄ IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell.

The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design.

This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology.

The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

The purpose of this paper is to assess the thermo-mechanical reliability of a solder bump with different underfills, with the evaluation of different underfill materials. As there is more demand in higher input/output, smaller package size and lower cost, a flip chip mounted at the module level of a board is considered. However, bonding large chips (die) to organic module means a larger differential thermal expansion mismatch between the module and the chip. To reduce the thermal stresses and strains at solder joints, a polymer underfill is added to fill the cavity between the chip and the module. This procedure has typically, at least, resulted in an increase of the thermal fatigue life by a factor of ten, as compared to the non-underfilled case. Yet, this particular case is to deal with a flip chip mounted on both sides of a printed circuit board (PCB) module symmetrically (solder bump interconnection with Cu-Pillar). Note that Cu-Pillar bumping is known to possess good electrical properties and better electromigration performance. The drawback is that the Cu-Pillar bump can introduce high stress due to the higher stiffness of Cu compared to the solder material.

As a reliability assessment, thermal cyclic loading condition was considered in this case. Thermal life prediction was conducted by using finite element analysis (FEA) and modified Darveaux’s model, considering microsize of the solder bump. In addition, thermo-mechanical properties of four different underfill materials were characterized, such as Young’s modulus at various temperatures, coefficient of temperature expansion and glass transition temperature. By implementing these properties into FEA, life prediction was accurately achieved and verified with experimental results.

The modified life prediction method was successfully adopted for the case of Cu-Pillar bump interconnection in flip chip on the module package. Using this method, four different underfill materials were evaluated in terms of material property and affection to the fatigue life. Both predicted life and experimental results are obtained.

This study introduces the technique to accurately predict thermal fatigue life for such a small scale of solder interconnection in a newly designed flip chip package. In addition, a guideline of underfill material selection was established by understanding its affection to thermo-mechanical reliability of this particular flip chip package structure.

This paper aims to realize the vertical interconnection in 3D radio frequency (RF) circuit by coaxial transitions with broad working bandwidth and small signal loss.

An advanced packaging method, 12-inch wafer-level through-mold-via (TMV) additive manufacturing, is used to fabricate a 3D resin-based coaxial transition with a continuous ground wall (named resin-coaxial transition). Designation and simulation are implemented to ensure the application universality and fabrication feasibility. The outer radius R of coaxial transition is optimized by designing and fabricating three samples.

The fabricated coaxial transition possesses an inner radius of 40 µm and a length of 200 µm. The optimized sample with an outer radius R of 155 µm exhibits S11 < –10 dB and S21 > –1.3 dB at 10–110 GHz and the smallest insertion loss (S21 = 0.83 dB at 77 GHz) among the samples. Moreover, the S21 of the samples increases at 58.4–90.1 GHz, indicating a broad and suitable working bandwidth.

The wafer-level TMV additive manufacturing method is applied to fabricate coaxial transitions for the first time. The fabricated resin-coaxial transitions show good performance up to the W-band. It may provide new strategies for novel designing and fabricating methods of RF transitions.

Bumpless Cu/SiO₂ hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s continuous development, which achieves the stacks of chips vertically connected via through-silicon via. Surface-activated bonding (SAB) and thermal-compression bonding (TCB) are used, but both have some shortcomings. The SAB method is overdemanding in the bonding environment, and the TCB method requires a high temperature to remove copper oxide from surfaces, which increases the thermal budget and grossly damages the fine-pitch device.

In this review, methods to prevent and remove copper oxidation in the whole bonding process for a lower bonding temperature, such as wet treatment, plasma surface activation, nanotwinned copper and the metal passivation layer, are investigated.

The cooperative bonding method combining wet treatment and plasma activation shows outstanding technological superiority without the high cost and additional necessity of copper passivation in manufacture. Cu/SiO₂ hybrid bonding has great potential to effectively enhance the integration density in future 3D packaging for artificial intelligence, the internet of things and other high-density chips.

To achieve heterogeneous bonding at a lower temperature, the SAB method, chemical treatment and the plasma-assisted bonding method (based on TCB) are used, and surface-enhanced measurements such as nanotwinned copper and the metal passivation layer are also applied to prevent surface copper oxide.

This paper aims to investigate Cu/SnAgCu/Cu transient liquid phase (TLP) bonding with different thicknesses for three-dimensional (3D) integrated circuit (IC).

This paper includes experiments and finite element simulation.

The growth rate of the intermetallic compound layer during TLP soldering was calculated to be 0.6 μm/s, and the small scallop-type morphology Cu₆Sn₅ grains can be observed. With the decrease in thickness in solder joint, the thickness of intermetallic compounds represents the same size and morphology, but the size of eutectic particles (Ag₃Sn, Cu₆Sn₅) in the matrix microstructure decrease obviously. It is found that with the increase in thickness, the tensile strength drops obviously. Based on finite element simulation, the smaller value of von Mises demonstrated that the more reliability of lead-free solder joints in 3D IC.

The Cu/SnAgCu/CuTLPbondingwithdifferentthicknessesfor3D IC was investigated.

Higher education institutions provide a vital role in providing education towards solving sustainability issues. Hence, the adoption of development agendas, such as the United Nations Sustainable Development Goals (SDGs) through the SDG Accord, into curriculum. As a signatory of the sector SDG Accord, Coventry University Group has the responsibility of providing an enabling environment to promote the achievement of the Goals. This article introduces a model for embedding the goals into curriculum; with creative teaching practice and enriching student experience at the centre to the approach taken. The approach considers three dimensions: Staff Development, the Goals within Teaching, and Students' Activities.

The purpose of this study is to offer the advanced leadless leadframe package which achieve small form factor and high thermal and electrical performance, according to the continuous market requirement. Because of demand and trends, new package structures that can accommodate many pins (I/Os) while maintaining the excellent thermal and electrical properties of the leadframe package was studied. Different from conventional leadframe and laminate packages, it must have the large-exposed pad for thermal dissipation and design flexibility to deploy signal, ground and power selectively.

In this study, the routable molded leadframe (rtMLF®) package applying the pre-resin MLF substrate was introduced. The structural advantages, in terms of design flexibility, were checked by adopting the specific electrical feature. Also, the excellence of thermal and electrical performance was confirmed by simulation. The sample was manufactured, and its package robustness was validated by reliability test.

rtMLF package that enables one layer substrate but routable pattern on top layer differently from existing leadframe package was developed and studied if it overcome the limitations of leadframe and laminate products. Asymmetric land layout was designed and special features to keep electrical interference was applied to prove design flexibility. The thermal and electrical simulation has been executed to check the advantages. And key differentiations were identified. Finally, actual sample was manufactured, and structural robustness was validated by package level and board level reliability.

The differentiation of new semiconductor package was introduced and its excellence was verified by electrical and thermal simulation as well as reliability test. It is expected to be adopted for alternative solutions not covered by the existing products.