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This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.

A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.

With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.

This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

In recent years, multiuser-multiple-input multiple-output (MU-MIMO)-based wireless communication system has emerged as a prominent 5G technique that has several advantages over conventional MIMO systems such as high data rate and channel capacity. In this paper, the authors introduce a novel low-complexity radix factorization-based fast Fourier transform (FFT) as a multibeamformer and maximal likelihood-MU detection (ML-MUD) techniques as an optimal signal subdetector which results with considerable complexity reduction with intolerable error rate performance.

The proposed radix-factorized FFT-multibeamforming (RF-FFT-MBF) architectures have the potential to reduce both hardware complexity and energy consumptions as compared to its state-of-the-art methods while meeting the throughput requirements of emerging 5G devices. Here through simulation results, the efficiency of the scaled ML subdetector system is compared with the conventional ML detectors.

Here through simulation results, the efficiency of the scaled ML subdetector system is compared with the conventional ML detectors. Through experimental results, it is well proved that the proposed detector offers significant hardware and energy efficiency with the least possible error rate performance overhead.

Here through simulation results, the efficiency of the scaled ML subdetector system is compared with the conventional ML detectors. Through experimental results, it is well proved that the proposed detector offers significant hardware and energy efficiency with the least possible error rate performance overhead.

The suggested work examines the latest developments such as the techniques employed for allocation of power, browser techniques, modern analysis and bandwidth efficiency of nonorthogonal multiple accesses (NOMA) in the network of 5G. Furthermore, the proposed work also illustrates the performance of NOMA when it is combined with various techniques of wireless communication namely network coding, multiple-input multiple-output (MIMO), space-time coding, collective communications, as well as many more. In the case of the MIMO system, the proposed research work specifically deals with a less complex recursive linear minimum mean square error (LMMSE) multiuser detector along with NOMA (MIMO-NOMA); here the multiple-antenna base station (BS) and multiple single-antenna users interact with each other instantaneously. Although LMMSE is a linear detector with a low intricacy, it performs poorly in multiuser identification because of the incompatibility between LMMSE identification and multiuser decoding. Thus, to obtain a desirable iterative identification rate, the proposed research work presents matching constraints among the decoders and identifiers of MIMO-NOMA.

To improve the performance in 5G technologies as well as in cellular communication, the NOMA technique is employed and contemplated as one of the best methodologies for accessing radio. The above-stated technique offers several advantages such as enhanced spectrum performance in contrast to the high-capacity orthogonal multiple access (OMA) approach that is also known as orthogonal frequency division multiple access (OFDMA). Code and power domain are some of the categories of the NOMA technique. The suggested research work mainly concentrates on the technique of NOMA, which is based on the power domain. This approach correspondingly makes use of superposition coding (SC) as well as successive interference cancellation (SIC) at source and recipient. For the fifth-generation applications, the network-level, as well as user-experienced data rate prerequisites, are successfully illustrated by various researchers.

The suggested combined methodology such as MIMO-NOMA demonstrates a synchronized iterative LMMSE system that can accomplish the optimized efficiency of symmetric MIMO NOMA with several users. To transmit the information from sender to the receiver, hybrid methodologies are confined to 2 × 2 as well as 4 × 4 antenna arrays, and thereby parameters such as PAPR, BER, SNR are analyzed and efficiency for various modulation strategies such as BPSK and QAM_j (j should vary from 8,16,32,64) are computed.

The proposed hybrid MIMO-NOMA methodologies are synchronized in terms of iterative process for optimization of LMMSE that can accomplish the optimized efficiency of symmetric for several users under different noisy conditions. From the obtained simulated results, it is found, there are 18%, 23% 16%, and 8% improvement in terms of Bit Error Rate (BER), Least Minimum Mean Squared Error (LMMSE), Peak to Average Power Ratio (PAPR), and capacity of channel respectively for Binary Phase Shift Key (BPSK) and Quadrature Amplitude Modulation (QAM) modulation techniques.

Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor.

A chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library.

The heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization.

Very few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.

This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD).

The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm.

The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps.

It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.

This conversation presents the reflections from five prominent disaster scholars and practitioners on the purpose of Radix – the Radical Disaster Interpretations network – as the authors celebrate its 20th anniversary.

This paper is based on the conversations that took place on Disasters: Deconstructed Podcast livestream on the 13th October 2021.

The conversation reflects on personal and professional journeys in disaster studies over the past 20 years and on what needs changing in order to make disaster interpretations more radical.

The conversation contributes to the ongoing discussions around explorations of radical pathways for understanding and preventing disasters.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

In most commercial processors, enhancing the speed of multiplication using radix-8 booth encoding is the preferred option. In radix-8 architecture, the 3X(= 2X + X) multiple generation is a major bottleneck. This paper aims to propose a parallel implementation scheme recognizing the symmetry in the carry recurrence equations of 3X multiples. The proposed architecture evaluates the odd (H) and even (K) carry signals separately. As prefix tree structure offers fast carry propagation, the parallel implementation is based on a hybrid style of two popular prefix architectures.

The performance of the proposed architecture is evaluated using Cadence TSMC 180 nm library. A comparison of performance parameters with other architectures has been carried out to highlight the architectural advantages of the proposed architecture.

A comparison of performance parameters with others shows that the proposed architecture has a reduced critical path and a commensurate improvement in delay for a bit width of 64. It is shown that up to 32 bits, this parallel architecture has a superior performance and would be the appropriate choice for Application Specific Integrated Circuit (ASIC) implementation. It has also been suggested that higher-order bit widths could be implemented using a modular arrangement.

This paper proposes a new parallel architecture for hard multiple (3X) generation in Radix-8 Booth encoding. As the multiplication is the key operation in digital signal processors, this type of high-speed architectures gains importance in the future processor design. Defence applications such as target finding and multiple target recognitions and image processing applications necessitate this type of high-speed multipliers. Also, it is appropriate for the ASIC implementation. The authors would like to mention that this paper is not yet published anywhere, and it is the research paper of Dr R. Nirmaladevi.

To address the problems of high performance computing by using the networks of workstations (NOW) and to discuss the complex performance evaluation of centralised and distributed parallel algorithms.

Defines the role of performance and performance evaluation methods using a theoretical approach. Presents concrete parallel algorithms and tabulates the results of their performance.

Sees that a network of workstations based on powerful personal computers belongs in the future and as very cheap, flexible and perspective asynchronous parallel systems. Argues that this trend will produce dynamic growth in the parallel architectures based on the networks of workstations.

We would like to continue these experiments in order to derive more precise and general formulae for typical used parallel algorithms from linear algebra and other application oriented parallel algorithms.

Describes how the use of NOW can provide a cheaper alternative to traditionally used massively parallel multiprocessors or supercomputers and shows the advantages of unifying the two disciplines that are involved.

Produces a new approach and exploits the parallel processing capability of NOW. Gives the concrete practical examples of the method that has been developed using experimental measuring.