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In most commercial processors, enhancing the speed of multiplication using radix-8 booth encoding is the preferred option. In radix-8 architecture, the 3X(= 2X + X) multiple generation is a major bottleneck. This paper aims to propose a parallel implementation scheme recognizing the symmetry in the carry recurrence equations of 3X multiples. The proposed architecture evaluates the odd (H) and even (K) carry signals separately. As prefix tree structure offers fast carry propagation, the parallel implementation is based on a hybrid style of two popular prefix architectures.

The performance of the proposed architecture is evaluated using Cadence TSMC 180 nm library. A comparison of performance parameters with other architectures has been carried out to highlight the architectural advantages of the proposed architecture.

A comparison of performance parameters with others shows that the proposed architecture has a reduced critical path and a commensurate improvement in delay for a bit width of 64. It is shown that up to 32 bits, this parallel architecture has a superior performance and would be the appropriate choice for Application Specific Integrated Circuit (ASIC) implementation. It has also been suggested that higher-order bit widths could be implemented using a modular arrangement.

This paper proposes a new parallel architecture for hard multiple (3X) generation in Radix-8 Booth encoding. As the multiplication is the key operation in digital signal processors, this type of high-speed architectures gains importance in the future processor design. Defence applications such as target finding and multiple target recognitions and image processing applications necessitate this type of high-speed multipliers. Also, it is appropriate for the ASIC implementation. The authors would like to mention that this paper is not yet published anywhere, and it is the research paper of Dr R. Nirmaladevi.

This paper aims to discuss problems, requirements and current trends for deploying group communication in real‐world scenarios from an integrated perspective.

The Hybrid Shared Tree is introduced – a new architecture and routing approach to combine network – and subnetwork‐layer multicast services in end‐system domains with transparent, structured overlays on the inter‐domain level.

The paper finds that The Hybrid Shared Tree solution is highly scalable and robust and offers provider‐oriented features to stimulate deployment.

A straightforward perspective is indicated in the paper for a mobility‐agnostic routing layer for future use.

The progress of parallel computing in Information Retrieval (IR) is reviewed. In particular we stress the importance of the motivation in using parallel computing for text retrieval. We analyse parallel IR systems using a classification defined by Rasmussen and describe some parallel IR systems. We give a description of the retrieval models used in parallel information processing. We describe areas of research which we believe are needed.

This article aims to explore how to incorporate similarity joins into XML database management systems (XDBMSs). The authors aim to provide seamless and efficient integration of similarity joins on tree-structured data into an XDBMS architecture.

The authors exploit XDBMS-specific features to efficiently generate XML tree representations for similarity matching. In particular, the authors push down a large part of the structural similarity evaluation close to the storage layer.

Empirical experiments were conducted to measure and compare accuracy, performance and scalability of the tree similarity join using different similarity functions and on the top of different storage models. The results show that the authors’ proposal delivers performance and scalability without hurting the accuracy.

Similarity join is a fundamental operation for data integration. Unfortunately, none of the XDBMS architectures proposed so far provides an efficient support for this operation. Evaluating similarity joins on XML is challenging, because it requires similarity matching on the text and structure. In this work, the authors integrate similarity joins into an XDBMS. To the best of the authors’ knowledge, this work is the first to leverage the storage scheme of an XDBMS to support XML similarity join processing.

The purpose of this study is to look into the three major new innovative components such as collection tree, tags cloud and geolocation for developing digital library system. This study aims to develop and design an integrated framework for enhancing this services.

This study will develop a single purpose-driven framework for the domain. It will vary user-friendly architecture on expanding the collection tree based on a high-level operating system and plugins. Now software programs are available in the Omeka Web repository. The whole integrated framework has been designed based on the Linux Operating platform and LAMP architecture towards depends on proper installation and configuration of the “Collection Tree” module with Omeka for both the administration and user interfaces.

With this integrated structure, keyword cloud users will have easy access to objects and full-text content. Because it can save readers time, the collection tree is helpful in them. This integrated framework for constructing and designing the collection tree for the digital library allows geolocation-based searches from multiple collections.

The integrated domain-specific framework has been designed and developed for the libraries. So, it is feasible to provide better library services in inter-operability and crosswalk through the Omeka collection tree interface. It increases the advanced search mechanism for users using this innovative module and techniques towards creating collection trees based on tag clouds and geolocation for library professionals and advanced level users from multiple collections of hierarchy.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

This article reviews some of the more unconventional text retrieval systems, emphasising those which have been commercialised. These sophisticated systems improve on conventional retrieval by using either innovative software or hardware to increase retrieval speed or functionality, precision or recall. The software systems reviewed are: AIDA, CLARIT, Metamorph, SIMPR, STATUS/IQ, TCS, TINA and TOPIC. The hardware systems reviewed are: CAFS‐ISP, the Connection Machine, GESCAN,HSTS,MPP, TEXTRACT, TRW‐FDF and URSA.

In the past, by adopting the handover prediction concept of the fast mobile IPv6, the authors have proposed a cross-layer architecture, which was called the proactive fast HCoP-B (FHCoP-B), to trigger layer 3 HCoP-B route optimization flow by 802.11 and 802.16 link events before the actual layer 2 handover of a mobile subnet in the nested mobile network (NEMO) occurs. In this way, proactive FHCoP-B has shortened its handover latency and packet loss. However, there are two scenarios where proactive FHCoP-B cannot normally complete its operations due to fast movements of the NEMO during handover. The paper aims to discuss these issues.

In this paper, the authors will propose efficient reactive FHCoP-B flows for these two scenarios to support fast and seamless handovers. The authors will further extend the analytical model proposed for mobile IPv6 to investigate four performance metrics of proactive and reactive FHCoP-B, HCoP-B and two well-known NEMO schemes with the radio link protocol (RLP), which can detect packet losses and performs retransmissions over the error-prone wireless link.

Through intensive simulations, the authors conclude that FHCoP-B outperforms HCoP-B and the other two well-known NEMO schemes by achieving the shortest handover latencies, the smallest number of packet losses and the fewest playback interruption time during handover only with few extra buffer spaces, even over error-prone wireless links of the nested NEMO.

This paper has three major contributions, which are rare in the NEMO literature. First, the proactive FHCoP-B has been enhanced as the reactive one to handle two fast handover scenarios with RLP for the nested NEMO. Second, the reactive FHCoP-B supports seamless reactive handover for the nested NEMO over error-prone wireless links. Third, mathematical performance analyses for two scenarios of reactive FHCoP-B with RLP over error-prone wireless links have been conducted.