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This study aims to propose a modified topology for an asymmetric multilevel inverter as a basic module that generates 13-level output voltage waveform. The basic module consists of eight switches (unidirectional and bidirectional switch) and four DC voltage sources with unequal magnitudes. The proposed topology reduces the number of switches, isolated DC sources, cost and size of the circuit significantly as compared to other topologies. In addition, the proposed circuit provides a modular structure for a multilevel inverter.

The proposed configuration is implemented through simulation and hardware development of a single-phase 13-level inverter prototype. A multicarrier-based pulse width modulation scheme is adopted for generating switching signals by using dSPACE real-time controller.

To demonstrate the advantages of the proposed configuration, a comparative analysis is carried out with other multilevel topologies in terms of number of switches, gate driver circuits, on-state switches and blocking voltage on the switches. The comparison results confirmed that the proposed configuration requires less number of components for the same number of voltage levels. Moreover, the peak inverse voltage on switches and losses is lower in the proposed configuration.

In the available literature, numerous topologies are presented with main emphasis on the reduced components count. In this study, the authors proposed a new topology for an asymmetrical source configuration. The performance of the proposed topology under steady-state and dynamic conditions is evaluated using simulation and experimental implementation.

This paper aims to propose Hidden Converter (H-Converter) combined with dual port 3Ø inverter for energy storage application to produce wide range of voltage. Some of the application required wide range of voltages, but problem from E-chopper is either boost or buck mode of operations, both modes are not possible. To overcome this drawback, H-Converter is combined with dual port 3Ø inverter controlled by carrier-based pulse width modulation (CB-PWM) technique is added with zero sequence injection.

Hidden converter is a bidirectional DC-DC chopper used to convert fixed DC to variable DC and vice versa in both buck and boost modes of operations. Dual port inverter is combined with hidden DC-DC converter can produce wide range of voltages.

The bidirectional DC-AC converter requires less power for processing and consumes less power losses by using modest carrier built- pulse width modulation scheme through proposed zero structure addition.

By using this proposed strategy H-Converter can produce wide range of voltage in both the sides and mostly power is processed in the 3Ø inverter with a one stage conversion with less power loss. As a result, with one stage power conversion has more efficiency because of less power loss. This proposed converter has designed by analysis, and the real time result is tested in an experiment.

The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA).

First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive.

In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively.

Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance.

This is the first time to realize all the function of a speed controller for IM drive within one FPGA.

The purpose of the paper is to develop high accurate and unified maximum power point tracking technique that tracks the maximum power from both the photovoltaic (PV) array and wind energy conversion system, (an unified maximum power point tracking technique implemented for both wind and solar sources to track maximum power with higher accuracy).

In recent times, multi-input Direct Current- Direct Current (DC-DC) converter has attracted attentiveness, to conserve more energy and to achieve more efficiency. The kinetic energy of the vehicle is converted to electrical energy and further stored into the battery, during the regenerative braking (moreover, the battery gets charged during the regenerative braking process by converting the kinetic energy of the vehicle into electrical energy). During such a process, only the pulse width modulation schemes of the inverter are changed. To charge electric vehicles (EVs), two renewable resources as solar and wind are combined to produce electric power. Therefore, it was conveyed that the EV will be continuously getting power without interruption using various sources and regenerated power.

The performance and effectiveness of the proposed system are studied by extensive simulations and (are) validated using a prototype of the system. The results prove that the proposed system achieves an efficiency of 95.2%, which is higher than that of the multi-input DC-DC converters existing in the literature.

A novel multi-input DC-DC landsman converter for powering plug-in hybrid electric vehicles (HEVs) is proposed in the research. This method proposes a new cost effective and efficient technique for HEVs with brushless DC motors. Wind power, battery and PV panel are used as the input sources for the proposed converter.

Industrial drives require appropriate control systems for reliable and efficient performance. With synchronous reluctance machines (SynRMs) slowly replacing the most commonly used induction, switched reluctance and permanent magnet machines, it is essential that the drive and its control be properly selected for enhanced performance. But the major drawback of synchronous reluctance motor is the presence of high torque ripple as its design is characterized by large number of variables. The solutions to reduce torque ripple include design modifications, choice of proper power electronic inverter and PWM strategy. But little has been explored about the power electronic inverters suited for synchronous reluctance motor drive to minimize torque ripple inherently by obtaining a more sinusoidal voltage. The purpose of this paper is to elaborate on the potential multilevel inverter topologies applicable to SynRM drives used in solar pumping applications.

The most significant field-oriented control using maximum torque per ampere algorithm for maximizing the torque production is used for the control of SynRM. Simulation results carried out using Matlab/Simulink are presented to justify the choice of inverter and its control technique for SynRM.

The five-level inverter drive gives lesser core or iron losses in the SynRMin comparison to the three- and two-level inverters due to lower Id current ripple. The five-level inverter reduces the torque ripple of the SynRM significantly in comparison to the three- and two-level inverter fed SynRM drives. The phase disposition-PWM control method used for the inverter shows the least total harmonic distortion (THD) levels in output voltage compared with the other level shifted PWM techniques.

Among the available topologies, a fitting topology is proposed for use for the SynRM drive to have minimal THD, minimal current and torque ripple. Additionally, this paper presents various modulation techniques available for the selected drive system and reports on a suitable technique based on minimal THD of output voltage and hence minimal torque ripple.

This paper presents and investigates a method named M×N‐ary chaotic pulse‐width‐position modulation (CPWPM) which is based on the combination of M‐ary chaotic pulse‐position modulation (CPPM) and N‐ary chaotic pulse‐width modulation (CPWM) in order to provide a better performance in noise‐affected environments as well as improve significantly bit rate.

Analysis of schemes for modulator and demodulator are presented in detail through describing the schemes of the individual methods and their combination. Theoretical evaluation of bit‐error rate (BER) performance in presence of additive white Gaussian noise (AWGN) is provided. Chaotic behavior with tent map in variation of modulation parameters is also investigated. In order to verify the theoretical analyses, numerical simulations are carried out and their results are reported.

Both evaluation and simulation results show that when the number of symbols increases, the bit rate is improved significantly but the BER performance is just slightly worse. This makes M×N‐ary CPWPM become an effective method for chaos‐based digital communication.

Although CPPM, CPWM and M‐ary modulation methods have been described in the literature separately, their combination is presented and investigated for the first time in this paper.

The design issues on network architecture and modulation scheme that can be used to implement reliable MIL‐STD‐1773 avionics optical fiber data buses are discussed. Both single‐star and multi‐star architectures are presented to such optical fiber data buses. Several network configurations based on passive and/or active coupling components are also considered, and they are compared in terms of system complexity and reliability. Moreover, three modulation schemes are presented, i.e. partial trilevel Manchester II bi‐phase coding, extended Manchester II bi‐phase coding with beginning‐stopping flags, and pseudo‐four‐ary pulse width modulation, respectively. Their use can feasibly solve the problem associated with fast identification of correct operation states of an active transmitter at the output of optical receivers.

These implementations not only generate excessive voltage levels to enhance the quality of power but also include a detailed investigating of the various modulation methods and control schemes for multilevel inverter (MLI) topologies. Reduced harmonic modulation technology is used to produce 11-level output voltage with the production of renewable energy applications. The simulation is done in the MATLAB/Simulink for 11-level symmetric MLI and is correlated with the conventional inverter design.

This paper is focused on investigating the different types of asymmetric, symmetric and hybrid topologies and control methods used for the modular multilevel inverter (MMI) operation. Classical MLI configurations are affected by performance issues such as poor power quality, uneconomic structure and low efficiency.

The variations in both carrier and reference signals and their performance are analyzed for the proposed inverter topologies. The simulation result compares unipolar and bipolar pulse-width modulation (PWM) techniques with total harmonic distortion (THD) results. The solar-fed 11-level MMI is controlled using various modulation strategies, which are connected to marine emergency lighting loads. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by using SPARTAN 3A field programmable gate array (FPGA) board and the least harmonics are obtained by improving the power quality.

The simulation result compares unipolar and bipolar PWM techniques with THD results. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by a SPARTAN 3A field programmable gate array (FPGA) board, and the power quality is improved to achieve the lowest harmonics possible.

This paper aims to develop a method for a unified model of pulse width modulation (PWM) voltage source inverters (VSI). This generic method, based on a common and easy-to-use carrier-based modulation, allows to generate the exhaustive solution set for a given PWM-VSI.

The use of the generalized inverse theory is developed to express the PWM solution set for the duty cycle. Indeed, the infinite number of PWM solutions is demonstrated. To explore this solution set, the unified model described exhibits degrees of freedom. The admissible margins to set the degree of freedom are highlighted. Some experimental results are presented.

It is demonstrated how the degree of freedom can be directly connected with efficiency indicators such as common mode voltage, inverter linearity and switching losses. The expression of the PWM solution set boundaries is clearly expressed.

Further studies should explore how the degree of freedom can be connected with parameters associated with the current (and not the voltage as described in this paper).

The paper includes implications for the development of a more generic approach for PWM multilevel VSI.

This paper fulfils a mathematical frame to ease the expression of PWM scheme.

Flying‐capacitor multilevel converters (FCC) need a passive or active regulation of the capacitor voltages. Recently the trend is towards active control, often implemented separately from the current control. The advantages of a true multi‐variable control sparked the interest to apply Model Based Predictive Control (MBPC) for FCC. In this paper an objective analysis method to evaluate the effects of several design choices is presented. The effects of the weight factor selection, model simplification, and prediction horizon expansion for MBPC of a 3‐level FCC are analyzed in a systematical way.

The analysis is mainly based on the mean square error (MSE) of current and capacitor voltage. The results are analysed for different lengths of the prediction horizon and for a wide range of weight factor values. Similarly the effect of a model simplification, neglecting the neutral point voltage, is studied when implementing MBPC for FCCs while considering the computational aspects. Validation of the simulation results is done by experiments on an FPGA‐based setup.

Including the effect of the neutral point voltage considerably increases the current control quality and a much wider range of good values for the weight factor exists. As this good range is not critically dependent on the current amplitude it is possible to select one weight factor value for all operating points. Furthermore, it is concluded that increasing the prediction horizon increases the computational load without improving the control quality.

The effects of increasing the prediction horizon when including other controlled variables is to be investigated, as well as the robustness to modeling errors. The MSE analysis methodology is very suitable for this further research.

For practitioners of MBPC in power electronics the paper proves that by means of simulations and the MSE one value for weight factor can be chosen for all operating points. The paper clearly shows that a practical implementation is feasible and demonstrates that neglecting the neutral point voltage is not good practice.

The MSE‐based analysis is shown to be a systematical and unbiased methodology to evaluate the effects of design choices. The results from this analysis can be directly applied in practical setups.