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Reduction in components using modified topology for asymmetrical multilevel inverter

Kanungo Barada Mohanty (Department of Electrical Engineering, National Institute of Technology, Rourkela, Odisha, India)
Kishor Thakre (Department of Electrical Engineering, National Institute of Technology, Rourkela, Odisha, India)
Aditi Chatterjee (Department of Electrical Engineering, National Institute of Technology, Rourkela, Odisha, India)
Ashwini Kumar Nayak (Department of Electrical Engineering, National Institute of Technology, Rourkela, Odisha, India)
Vinaya Sagar Kommukuri (Department of Electrical Engineering, National Institute of Technology, Rourkela, Odisha, India)

World Journal of Engineering

ISSN: 1708-5284

Article publication date: 2 April 2019

Issue publication date: 12 April 2019

79

Abstract

Purpose

This study aims to propose a modified topology for an asymmetric multilevel inverter as a basic module that generates 13-level output voltage waveform. The basic module consists of eight switches (unidirectional and bidirectional switch) and four DC voltage sources with unequal magnitudes. The proposed topology reduces the number of switches, isolated DC sources, cost and size of the circuit significantly as compared to other topologies. In addition, the proposed circuit provides a modular structure for a multilevel inverter.

Design/methodology/approach

The proposed configuration is implemented through simulation and hardware development of a single-phase 13-level inverter prototype. A multicarrier-based pulse width modulation scheme is adopted for generating switching signals by using dSPACE real-time controller.

Findings

To demonstrate the advantages of the proposed configuration, a comparative analysis is carried out with other multilevel topologies in terms of number of switches, gate driver circuits, on-state switches and blocking voltage on the switches. The comparison results confirmed that the proposed configuration requires less number of components for the same number of voltage levels. Moreover, the peak inverse voltage on switches and losses is lower in the proposed configuration.

Originality/value

In the available literature, numerous topologies are presented with main emphasis on the reduced components count. In this study, the authors proposed a new topology for an asymmetrical source configuration. The performance of the proposed topology under steady-state and dynamic conditions is evaluated using simulation and experimental implementation.

Keywords

Citation

Mohanty, K.B., Thakre, K., Chatterjee, A., Nayak, A.K. and Kommukuri, V.S. (2019), "Reduction in components using modified topology for asymmetrical multilevel inverter", World Journal of Engineering, Vol. 16 No. 1, pp. 71-77. https://doi.org/10.1108/WJE-01-2017-0010

Publisher

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Emerald Publishing Limited

Copyright © 2019, Emerald Publishing Limited

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