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The purpose of this paper is to investigate the effect of high-k material HfO₂ as a buffer layer for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate.

RF-sputtered Pb[Zr0.35Ti0.65]O₃ or (PZT) and plasma-enhanced atomic layer deposited HfO₂ films were selected as the ferroelectric and high-k buffer layer, respectively, for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Multiple angle ellipsometry and X-ray diffraction analysis was carried out to obtain the crystal orientation, refractive index and absorption coefficient parameters of the deposited/annealed films. In the different range of annealing temperature, the refractive index was observed in the range of 2.9 to 2 and 1.86 to 2.64 for the PZT and HfO₂ films, respectively

Electrical and ferroelectric properties of the dielectric and ferroelectric films and their stacks were obtained by fabricating the metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal, metal/insulator/silicon and MFeIS capacitor structures. A closed hysteresis loop with remnant polarization of 4.6 µC/cm² and coercive voltage of 2.1 V was observed in the PZT film annealed at 5000 C. Introduction of HfO₂ buffer layer (10 nm) improves the memory window from 5.12 V in MFeS to 6.4 V in MFeIS structure with one order reduction in the leakage current density. The same MFeS device was found having excellent fatigue resistance property for greater than 1010 read/write cycles and data retention time more than 3 h.

The MFeIS structure has been fabricated with constant PZT thickness and varied buffer layer (HfO₂) thickness. Electrical characteristics shows the improved leakage current and memory window in the MFeIS structures as compared to the MFeS structures. Optimized MFeIS structure with 10-nm buffer layer shows the excellent ferroelectric properties with endurance greater than E10 read/write cycles and data retention time higher than 3 h. The above properties indicate the MFe(100 nm)I(10 nm)S gate stack as a potential candidate for the FeFET-based nonvolatile memory applications.

Development of (1T-type) ferroelectric random access memory (FeRAM) has most actively progressed since 1995 and motivated by the physical limits and technological drawbacks of the flash memory. 1T-type FeRAM implements ferroelectric layer at the field effect transistor (FET) gate. During the course of the investigation, it was very difficult to form a thermodynamically stable ferroelectric-semiconductor interface at the FET gate, leading to the introduction of one insulating buffer layer between the ferroelectric and the silicon substrate to overcome this problem. In this study, Al₂O₃ a high-k buffer layer deposited by plasma enhanced atomic layer deposition (PEALD) is sandwiched between the ferroelectric layer and silicon substrate.

Ferroelectric/high-k gate stack were fabricated on the silicon substrate and pt electrode. Structural characteristics of the ferroelectric (PZT) and high-k (Al₂O₃) thin film deposited by RF sputtering and PEALD, respectively, were optimized and investigated for different process parameters. Metal/PZT/Metal, Metal/PZT/Silicon, Metal/PZT/Al₂O₃/Silicon structures were fabricated and electrically characterized to obtain the memory window, leakage current, hysteresis, PUND, endurance and breakdown characteristics.

XRD pattern shows the ferroelectric perovskite thin Pb[Zr_0.35Ti_0.65]O₃ film with (101) tetragonal orientation deposited by sputtering and PEALD Al₂O₃ with (312) orientation showing amorphous nature. Multiple angle analysis shows that the refractive index of PZT varies from 2.248 to 2.569, and PEALD Al₂O₃ varies from 1.6560 to 1.6957 with post-deposition annealing temperature. Increase in memory window from 2.3 to 8.4 V for the Metal-Ferroelectric-Silicon (MFS) and Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure has been observed at the annealing temperature of 500°C. MFIS structure with 10 nm buffer layer shows excellent endurance of 3 × 109 read-write cycles and the breakdown voltage of 33 V.

This paper shows the feature, principle and improvement in the electrical properties of the fabricated gate stack for 1T-type nonvolatile FeFET. The insulating buffer layer sandwiched between ferroelectric and silicon substrate acts as a barrier to ferroelectric–silicon interdiffusion improves the leakage current, memory window, endurance and breakdown voltage. This is perhaps the first time that the combination of sputtered PZT on the PEALD Al₂O₃ layer is being reported.

The purpose of this paper is to demonstrate industrial Internet of Things (IIoT) solution to improve the equipment condition monitoring with equipment status data and process condition monitoring with plasma optical emission spectroscopy data, simultaneously. The suggested research contributes e-maintenance capability by remote monitoring in real time.

Semiconductor processing equipment consists of more than a thousand of components, and unreliable condition of equipment parts leads to the failure of wafer production. This study presents a web-based remote monitoring system for physical vapor deposition (PVD) systems using programmable logic controller (PLC) and Modbus protocol. A method of obtaining electron temperature and electron density in plasma through optical emission spectroscopy (OES) is proposed to monitor the plasma process. Through this system, parts that affect equipment and processes can be controlled and properly managed. It is certainly beneficial to improve the manufacturing yield by reducing errors from equipment parts.

A web-based remote monitoring system provides much of benefits to equipment engineers to provide equipment data for the equipment maintenance even though they are physically away from the equipment side. The usefulness of IIoT for the e-maintenance in semiconductor manufacturing domain with the in situ monitoring of plasma parameters is convinced. The authors found the average electron temperature gradually with the increase of Ar carrier gas flow due to the increased atomic collisions in PVD process. The large amount of carrier gas flow, in this experimental case, was 90 sccm, dramatically decreasing the electron temperature, which represents kinetic energy of electrons.

Semiconductor industries require high level of data security for the protection of their intellectual properties, and it also falls into equipment operational condition; however, data security through the Internet communication is not considered in this research, but it is already existing technology to be easily adopted by add-on feature.

The findings indicate that crucial equipment parameters are the amount of carrier gas flow rate and chamber pressure among the many equipment parameters, and they also affect plasma parameters of electron temperature and electron density, which directly affect the quality of metal deposition process result on wafer. Increasing the gas flow rate beyond a certain limit can yield the electron temperature loss to have undesired process result.

Several research studies on data mining with semiconductor equipment data have been suggested in semiconductor data mining domain, but the actual demonstration of the data acquisition system with real-time plasma monitoring data has not been reported. The suggested research is also valuable in terms of high cost and complicated equipment manufacturing.

This study aims to investigate the effect of temperature applied at the initial deposition of Aluminium Nitride (AlN) thin-film on a silicon substrate by high-power impulse magnetron sputtering (HiPIMS) technique.

HiPIMS system was used to deposit AlN thin film at a low output power of 200 W. The ramping temperature was introduced to substrate from room temperature to maximum 100°Cat the initial deposition of thin-film, and the result was compared to thin-film sputtered with no additional heat. For the heat assistance AlN deposition, the substrate was let to cool down to room temperature for the remaining deposition time. The thin-films were characterized by X-ray diffraction (XRD) and atomic force microscope (AFM) while the MIS Schottky diode characteristic investigated through current-voltage response by a two-point probe method.

The XRD pattern shows significant improvement of the strong peak of the c-axis (002) preferred orientation of the AlN thin-film. The peak was observed narrowed with temperature assisted where FWHM calculated at 0.35° compared to FWHM of AlN thin film deposited at room temperature at around 0.59°. The degree of crystallinity of bulk thin film was improved by 28% with temperature assisted. The AFM images show significant improvement as low surface roughness achieved at around 0.7 nm for temperature assisted sample compares to 3 nm with no heat applied.

The small amount of heat introduced to the substrate has significantly improved the growth of the c-axis AlN thin film, and this method is favorable in the deposition of the high-quality thin film at the low-temperature process.

The purpose of this study is to prepare a state-of-the-art review on advanced ceramic materials including their fabrication techniques, characteristics, applications and wettability.

This review paper presents the various types of advanced ceramic materials according to their compounding elements, fabrication techniques of advanced ceramic powders as well as their consolidation, their characteristics, applications and wetting properties. Hydrophobic/hydrophilic properties of advanced ceramic materials are described in the paper with their state-of-the-art application areas. Optical properties of fine ceramics with their intrinsic characteristics are also presented within. Special focus is given to the brief description of application-based manipulation of wetting properties of advanced ceramics in the paper.

The study of wetting/hydrophobicity/hydrophilicity of ceramic materials is important by which it can be further modified to achieve the required applications. It also makes some sense that the material should be tested for its wetting properties when it is going to be used in some important applications like biomedical and dental. Also, these advanced ceramics are now often used in the fabrication of filters and membranes to purify liquid/water so the study of wetting characteristics of these materials becomes essential. The optical properties of advanced ceramics are equally making them suitable for many state-of-the-art applications. Dental, medical, imaging and electronics are the few sectors that use advanced ceramics for their optical properties.

This review paper includes various advanced ceramic materials according to their compounding elements, different fabrication techniques of powders and their consolidation, their characteristics, various application area and hydrophobic/hydrophilic properties.

Al₂O₃ used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of traps at interface and in bulk which causes serious threat is necessary for better performance. The purpose of this paper is to investigate the effect of post-deposition rapid thermal annealing (PDA) and post-metallization annealing (PMA) on the structural and electrical characteristics of Pd/Al2O3/6H-SiC capacitors.

Al₂O₃ film is deposited by ALD; PDA is performed by rapid thermal annealing (RTA) in N₂ at 900°C for 1 min and PMA in forming gas for 10 and 40 min. X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements data are studied in addition to capacitance-voltage (C-V) and current-voltage (I-V) characteristics for the fabricated Pd/Al₂O₃/SiC capacitors. Conduction mechanism contributing to the gate leakage current is extracted for the entire range of gate electric field.

RTA forms aluminum silicide at the interface causing an increase in the density of the interface states and gate leakage current for devices with an annealed film, when compared with an as-deposited film. One order improvement in leakage current has been observed for the devices with RTA, after subjecting to PMA for 40 min, compared with those devices for which PMA was carried out for 10 min. Whereas, no improvement in leakage current has been observed for the devices on as-deposited film, even after subjecting to PMA for 40 min. Conduction mechanisms contributing to gate leakage current are extracted for the investigated Al₂O₃/SiC capacitors and are found to be trapfilled limit process at low-field regions; trapassisted tunneling in the mid-field regions and Fowler–Nordheim (FN) tunneling are dominating in high-field regions.

The effect of PDA and PMA on the structural and electrical characteristics of Pd/Al₂O₃/SiC capacitors suitable for flash memory applications is investigated in this paper.

The processing techniques and materials utilized in the fabrication of a two-terminal electrostatically actuated micro-electro-mechanical cantilever-arrayed device used for radio frequency tuning applications are presented in this work. The paper aims to discuss these issues.

The process, which is based on silicon surface micromachining, uses spin-coated photoresist as the sacrificial layer underneath the electroplated gold structural material and an insulating layer of silicon dioxide, deposited using plasma enhanced chemical vapour deposition (PECVD), to avoid a short circuit between the cantilever and the bottom electrode in a total of six major fabrication steps. These included the PECVD of the silicon dioxide insulating layer, optical lithography to transfer photomask layer patterns, vacuum evaporation to deposit thin films of titanium (Ti) and gold (Au), electroplating of Au, the dry release of the cantilever beam arrays, and finally the wafer dicing to split the different micro devices. These process steps were each sub-detailed to give a total of 14 micro-fabrication processes.

Scanning electron microscope images taken on the final fabricated device that was dry released using oxygen plasma ashing to avoid stiction showed 12 freely suspended micro-cantilevered beams suspended with an average electrostatic gap of 2.29±0.17 μm above a 4,934±3 Å thick silicon dioxide layer. Preliminary dimensional measurements on the fabricated devices revealed that the cantilevers were at least 52.06±1.93 μm wide with lengths varying from 377.97±0.01 to 1,491.89±0.01 μm and were at least 2.21±0.05 μm thick.

The cantilever beams used in this work were manufactured using electroplated gold, and photoresist was used as a sacrificial layer underneath the beams. Plasma ashing was used to release the beams. The beams were anchored to a central electrode and each beam was designed with varying length.

This paper aims to analyse the influence of the thickness of different layers [diamond-like-carbon (DLC) and chromium nitride (CrN)] on the sliding wear behaviour of a multifunctional coating on AISI 1020 substrates. When small and cheap components need to be manufactured in large scale, they are often produced using soft metals, such as unhardened low carbon steels and pure iron.

Two families, one with thicker films and the other with thinner films, were deposited onto a soft carbon steel substrate by plasma-enhanced chemical vapour deposition (PECVD). Reciprocating linear tests with incremental loading assessed the durability of the coatings. In addition, friction coefficient and wear rates of both specimens and counterbodies were measured at a constant load.

Thinner layers presented lower sliding wear rates (four-five times lower) for both specimens and counterbodies, less spalling and protective tribolayers on the wear tracks.

Although multilayered CrN–DLC coatings on relatively hard substrates such as HSS and cemented carbide tools are already a proven technology, much less is known about its deposition on a much softer substrate such as low carbon steel. In previous works, we have analysed the influence of layer thickness on hardness and scratch resistance of the same coatings. This paper presents results for their performance under wear sliding conditions using an original approach (three-dimensional triboscopic maps) for two distinct configurations (increasing load and constant load).

The purpose of this paper is to present a comprehensive review on development and future trends in zinc oxide thin film transistors (ZnO TFTs). This paper presents the development of TFT technology starting from amorphous silicon, poly-Si to ZnO TFTs. This paper also discusses about transport and device modeling of ZnO TFT and provides a comparative analysis with other TFTs on the basis of performance parameters.

It highlights the need of high–k dielectrics for low leakage and low threshold voltage in ZnO TFTs. This paper also explains the effect of grain boundaries, trap densities and threshold voltage shift on the performance of ZnO TFT. Moreover, it also addresses the challenges like requirement of stable p-type ZnO semiconductor for various electronic applications and high value of ZnO mobility to meet growing demand of high-definition light emitting diode TV (HD-LED TV).

This review will motivate the readers to further investigate the conduction mechanism, best alternate for gate-dielectric and the deposition technique optimization for the enhancement of the performance of ZnO TFTs.

This is a literature review. The technological evolution of TFT in general and ZnO TFT in particular is presented in this paper.

The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel.

During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature.

Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry.

Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch.

The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.