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Al₂O₃ used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of traps at interface and in bulk which causes serious threat is necessary for better performance. The purpose of this paper is to investigate the effect of post-deposition rapid thermal annealing (PDA) and post-metallization annealing (PMA) on the structural and electrical characteristics of Pd/Al2O3/6H-SiC capacitors.

Al₂O₃ film is deposited by ALD; PDA is performed by rapid thermal annealing (RTA) in N₂ at 900°C for 1 min and PMA in forming gas for 10 and 40 min. X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements data are studied in addition to capacitance-voltage (C-V) and current-voltage (I-V) characteristics for the fabricated Pd/Al₂O₃/SiC capacitors. Conduction mechanism contributing to the gate leakage current is extracted for the entire range of gate electric field.

RTA forms aluminum silicide at the interface causing an increase in the density of the interface states and gate leakage current for devices with an annealed film, when compared with an as-deposited film. One order improvement in leakage current has been observed for the devices with RTA, after subjecting to PMA for 40 min, compared with those devices for which PMA was carried out for 10 min. Whereas, no improvement in leakage current has been observed for the devices on as-deposited film, even after subjecting to PMA for 40 min. Conduction mechanisms contributing to gate leakage current are extracted for the investigated Al₂O₃/SiC capacitors and are found to be trapfilled limit process at low-field regions; trapassisted tunneling in the mid-field regions and Fowler–Nordheim (FN) tunneling are dominating in high-field regions.

The effect of PDA and PMA on the structural and electrical characteristics of Pd/Al₂O₃/SiC capacitors suitable for flash memory applications is investigated in this paper.

The purpose of this paper is to electrically examine the quality of thin thermally grown SiO₂ with thickness variation, on Si‐face of 4H‐SiC <0001> (having 50 μm epitaxial layer) by current‐voltage (I‐V) and capacitance‐voltage (C‐V) methods.

Metal‐oxide‐silicon carbide (MOSiC) structures with varying oxide thickness have been fabricated on device grade 4H‐SiC substrate. Ni has been used for gate metal on thermally oxidized Si‐face and a composite layer of Ti‐Au has been used for Ohmic contact on the highly doped C‐face of the substrate. Each structure was diced and bonded on a TO‐8 header with a suitable wire bonding for further testing using in‐house developed LabVIEW‐based computer aided measurement setup.

The leakage current of fabricated structures shows an asymmetric behavior with the polarity of gate bias ( + V or −V at the anode). A strong relation of oxide thickness and temperature on effective barrier height at SiO₂/4H‐SiC interface as well as on oxide charges have been established and reported in this paper.

The paper focuses on the development of 4H‐SiC based device technology in the fabrication of MOSiC‐based integrated structures.

The present experiments are intended to help characterize defects in very thin MOS oxide and at its Si/SiO₂ interface using a temperature‐dependent electrical characterization method, high low temperature capacitance voltage method and, especially, to investigate high temperature range. Oxide‐fixed traps are differentiated from slow‐state traps and from fast‐state traps by evaluating their electrical behaviour at different temperatures. The analysis points out the excess current after Fowler Nordheim electron injection based on hole generation, trapping, and hopping transport at high temperatures. The defect relaxation property versus temperature is investigated and defect relaxation activation energies are calculated. Creation mechanisms of interface states are especially identified by injection at different temperatures and these are compared with the other two kinds of defects. Fast‐state traps and all defect cross‐sections are calculated along and their creation activation energies are determined from Arrhenius plots.

This paper aims to investigate the effects of different ultrasonic-assisted loading degrees on the microstructure, mechanical properties and the fracture morphology of Cu/Zn+15%SAC0307+15%Cu/Al solder joints.

A new method in which 45 μm Zn particles were mixed with 15% 500 nm Cu particles and 15% 500 nm SAC0307 particles as solders (SACZ) and five different ultrasonic loading degrees were applied for realizing the soldering between Cu and Al at 240 °C and 8 MPa. Then, SEM was used to observe and analyze the soldering seam, interface microstructure and fracture morphology; the structural composition was determined by EDS; the phase of the soldering seam was characterized by XRD; and a PTR-1102 bonding tester was adopted to test the average shear strength.

The results manifest that Al–Zn solid solution is formed on the Al side of the Cu/SACZ/Al joints, while the interface IMC (Cu₅Zn₈) is formed on the Cu side of the Cu/SACZ/Al joints. When single ultrasonic was used in soldering, the interface IMC (Cu₅Zn₈) gradually thickens with the increase of ultrasonic degree. It is observed that the proportion of Zn or ZnO areas in solders decreases, and the proportion of Cu–Zn compound areas increases with the variation of ultrasonic degree. The maximum shear strength of joint reaches 46.01 MPa when the dual ultrasonic degree is 60°. The fracture position of the joint gradually shifts from the Al side interface to the solders and then to the Cu side interface.

The mechanism of ultrasonic action on micro-nanoparticles is further studied. By using different ultrasonic loading degrees to realize Cu/Al soldering, it is believed that the understandings gained in this study may offer some new insights for the development of low-temperature soldering methodology for heterogeneous materials.