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Development of (1T-type) ferroelectric random access memory (FeRAM) has most actively progressed since 1995 and motivated by the physical limits and technological drawbacks of the flash memory. 1T-type FeRAM implements ferroelectric layer at the field effect transistor (FET) gate. During the course of the investigation, it was very difficult to form a thermodynamically stable ferroelectric-semiconductor interface at the FET gate, leading to the introduction of one insulating buffer layer between the ferroelectric and the silicon substrate to overcome this problem. In this study, Al₂O₃ a high-k buffer layer deposited by plasma enhanced atomic layer deposition (PEALD) is sandwiched between the ferroelectric layer and silicon substrate.

Ferroelectric/high-k gate stack were fabricated on the silicon substrate and pt electrode. Structural characteristics of the ferroelectric (PZT) and high-k (Al₂O₃) thin film deposited by RF sputtering and PEALD, respectively, were optimized and investigated for different process parameters. Metal/PZT/Metal, Metal/PZT/Silicon, Metal/PZT/Al₂O₃/Silicon structures were fabricated and electrically characterized to obtain the memory window, leakage current, hysteresis, PUND, endurance and breakdown characteristics.

XRD pattern shows the ferroelectric perovskite thin Pb[Zr_0.35Ti_0.65]O₃ film with (101) tetragonal orientation deposited by sputtering and PEALD Al₂O₃ with (312) orientation showing amorphous nature. Multiple angle analysis shows that the refractive index of PZT varies from 2.248 to 2.569, and PEALD Al₂O₃ varies from 1.6560 to 1.6957 with post-deposition annealing temperature. Increase in memory window from 2.3 to 8.4 V for the Metal-Ferroelectric-Silicon (MFS) and Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure has been observed at the annealing temperature of 500°C. MFIS structure with 10 nm buffer layer shows excellent endurance of 3 × 109 read-write cycles and the breakdown voltage of 33 V.

This paper shows the feature, principle and improvement in the electrical properties of the fabricated gate stack for 1T-type nonvolatile FeFET. The insulating buffer layer sandwiched between ferroelectric and silicon substrate acts as a barrier to ferroelectric–silicon interdiffusion improves the leakage current, memory window, endurance and breakdown voltage. This is perhaps the first time that the combination of sputtered PZT on the PEALD Al₂O₃ layer is being reported.

The purpose of this paper is to investigate the effect of high-k material HfO₂ as a buffer layer for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate.

RF-sputtered Pb[Zr0.35Ti0.65]O₃ or (PZT) and plasma-enhanced atomic layer deposited HfO₂ films were selected as the ferroelectric and high-k buffer layer, respectively, for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Multiple angle ellipsometry and X-ray diffraction analysis was carried out to obtain the crystal orientation, refractive index and absorption coefficient parameters of the deposited/annealed films. In the different range of annealing temperature, the refractive index was observed in the range of 2.9 to 2 and 1.86 to 2.64 for the PZT and HfO₂ films, respectively

Electrical and ferroelectric properties of the dielectric and ferroelectric films and their stacks were obtained by fabricating the metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal, metal/insulator/silicon and MFeIS capacitor structures. A closed hysteresis loop with remnant polarization of 4.6 µC/cm² and coercive voltage of 2.1 V was observed in the PZT film annealed at 5000 C. Introduction of HfO₂ buffer layer (10 nm) improves the memory window from 5.12 V in MFeS to 6.4 V in MFeIS structure with one order reduction in the leakage current density. The same MFeS device was found having excellent fatigue resistance property for greater than 1010 read/write cycles and data retention time more than 3 h.

The MFeIS structure has been fabricated with constant PZT thickness and varied buffer layer (HfO₂) thickness. Electrical characteristics shows the improved leakage current and memory window in the MFeIS structures as compared to the MFeS structures. Optimized MFeIS structure with 10-nm buffer layer shows the excellent ferroelectric properties with endurance greater than E10 read/write cycles and data retention time higher than 3 h. The above properties indicate the MFe(100 nm)I(10 nm)S gate stack as a potential candidate for the FeFET-based nonvolatile memory applications.

After working through the case and assignment questions, students will be able to understand the following: the functioning of the microfinance institutions (MFIs); how the importance of using information technology (IT) can generate a competitive edge; and how emergent technologies, business analytics play a significant role in the expansion of business by helping in decision-making and meet up the corporate social responsibility by ethical disposal of electronic waste.

Fusion Microfinance Private Limited is a start-up company with a vision to build a professionally managed MFI that can achieve a healthy amalgamation of social and financial sustainability. It is operational in the less penetrated North Central part of India spread across four states (Madhya Pradesh, Uttarakhand, Uttar Pradesh and Delhi). Fusion appreciated the importance of IT and gradually leveraged IT to help the automation of various functions. Fusion wants to further optimize the organizational outreach to its rural clients by integrating its core function with IT. IT facilitates its huge client network conveniently with the usage of IT. Fusion also aims further to reduce its carbon footprint, thus moving towards the goal of achieving environmental sustainability through IT.

Undergraduate- or graduate-level course on management information systems, environmental sustainability or emergent technologies.

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CSS 1: Accounting and Finance.

The purpose of this study was to deposit Bi₄Ti₃O₁₂ films by electron gun evaporation technique starting from Bi_3.25La_0.75Ti₃O₁₂ as a target without annealing. The films have been deposited on Si(100), on thin film buffer layer of Pt and glass substrates. X-ray diffraction (XRD) was used to analyze structure of the films, which possesses a good structure with (0010) preferred orientation. Electronic behavior of the samples has been studied.

The dependence of both the structure and quality of the BLT thin films on different substrates is studied using XRD. The electrical characteristics were determined using capacitance–voltage (C–V) and current–voltage (I–V) measurements at the frequency of 1 MHz. Optical properties of the grown films deposited on glass substrates were characterized by optical transmittance measurements (UV-Vis).

The XRD analysis approved the crystallographer structure of the prepared Bi₄Ti₃O₁₂ films. The optical properties of deposited film (transmittance and the band gap value) are extracted by UV-Vis spectrum.

High crystalline quality Bi₄Ti₃O₁₂ films have been obtained using different substrates at room temperature by means of electron gun deposition. The electrical and ferroelectric properties of thin films were studied using I–V and C–V measurements. The band gap has been found to be about 3.62 eV for the studied film deposited on glass substrate. Electron beam evaporation technique is the most interesting methods, once considering many advantages; such as its stability, reproducibility, high deposition rate and the compositions of the films are controlled.