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Article
Publication date: 7 August 2017

T.K. Gupta, A.K. Pandey and O.P. Meena

This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage

Abstract

Purpose

This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current.

Design/methodology/approach

In this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits.

Findings

The result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits.

Originality/value

The research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.

Details

Circuit World, vol. 43 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 1 January 2008

Jian‐hong Yang, Gui‐fang Li and Hui‐lan Liu

Choosing suitable high‐K gate dielectrics to reduce the off‐state leakage (Ioff) by edge direct tunneling mechanism, demonstrating that the decreased Ioff increase significantly…

Abstract

Purpose

Choosing suitable high‐K gate dielectrics to reduce the off‐state leakage (Ioff) by edge direct tunneling mechanism, demonstrating that the decreased Ioff increase significantly when the gate dielectrics permittivity are above 25. The purpose of this paper is to report that HfSiON and HfLaO are promising gate dielectrics.

Design/methodology/approach

The off‐state gate current, drain current, and substrate current are investigated. The IdVgs characteristics for the 50 and 90 nm NMOSFET with various gate dielectrics are studied. Edge direct tunneling current (IEDT) with various gate dielectrics including SiO2, Si3N4 and HfO2 are compared and this paper also examines the IEDT with HfSiON and HfLaO gate dielectrics.

Findings

IEDT prevails over conventional gate‐induced drain‐leakage current (IGIDL), subthreshold leakage current (ISUB), band‐to‐band tunneling current (IBTBT) and it dominates off‐state leakage current. A large increase in off‐state leakage current occurs for smaller devices due to increase in IEDT at high Vdd. Although IEDT is decreased with increase in gate dielectrics permittivity K. The authors found fringing induced barrier lowering (FIBL) which could introduce significant off‐state leakage current for K>25. Fortunately, the IEDT with HfSiON and HfLaO gate dielectrics which are two‐five orders of magnitude lower than that of SiO2, furthermore, FIBL for HfSiON and HfLaO gate dielectrics are inconspicuous. Moreover, HfLaO and HfSiON have superior electrical performance and thermal stability.

Originality/value

Both edge direct tunneling and FIBL are considered to alternate high‐K gate dielectrics for nano‐scale MOSFET.

Details

Microelectronics International, vol. 25 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 8 March 2018

Amit Kumar Pandey, Tarun Kumar Gupta and Pawan Kumar Verma

This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

Abstract

Purpose

This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

Design/methodology/approach

In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.

Findings

The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.

Originality/value

The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

Article
Publication date: 23 January 2009

Balwinder Raj, A.K. Saxena and S. Dasgupta

The aim of this paper is to formulate the effect of the process variation on various leakage currents and subthreshold swing factor in FinFET devices. These variations cause a…

Abstract

Purpose

The aim of this paper is to formulate the effect of the process variation on various leakage currents and subthreshold swing factor in FinFET devices. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies.

Design/methodology/approach

Owing to large temperature variation within the die, the authors investigate the variation of various leakage currents with absolute die temperature.

Findings

The results obtained on the basis of the model are compared and contrasted with reported numerical and experimental results. A close match was found which validates the analytical approach.

Originality/value

The analytical modeling of subthreshold leakage current, subthreshold swing, gate leakage current and its variation with process parameters are carried out in this paper.

Details

Microelectronics International, vol. 26 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 9 August 2011

Ashwani K. Rana, Narottam Chand and Vinod Kapoor

The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE).

Abstract

Purpose

The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE).

Design/methodology/approach

A computationally efficient model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET in nano scale is presented. The model predictions are compared with the two‐dimensional Sentaurus device simulation.

Findings

Good agreement between the model and experimental data was obtained. The model also shows good agreement when compared with Sentaurus simulation and available model. It is observed that neglecting NSE may lead to large error in the calculated gate tunneling current. The findings provide a guideline to the severity of NSE from the point of view of standby power consumption. It is found that temperature and substrate bias have almost negligible effect on gate tunneling current. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed.

Research limitations/implications

The present work is concentrated only on the gate leakage current and is useful for gate leakage analysis of the circuits.

Practical implications

The model so developed is conceptually simple, numerically efficient and can be used for circuit simulator.

Originality/value

NSE are considered while modeling the gate tunneling current through nano scale n‐channel MOSFET.

Details

Multidiscipline Modeling in Materials and Structures, vol. 7 no. 2
Type: Research Article
ISSN: 1573-6105

Keywords

Article
Publication date: 23 July 2020

Sandeep Garg and Tarun Kumar Gupta

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and…

Abstract

Purpose

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

Design/methodology/approach

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

Findings

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

Originality/value

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

Details

Circuit World, vol. 47 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 3 April 2018

Papanasam E. and Binsu J. Kailath

Al2O3 used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of…

Abstract

Purpose

Al2O3 used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of traps at interface and in bulk which causes serious threat is necessary for better performance. The purpose of this paper is to investigate the effect of post-deposition rapid thermal annealing (PDA) and post-metallization annealing (PMA) on the structural and electrical characteristics of Pd/Al2O3/6H-SiC capacitors.

Design/methodology/approach

Al2O3 film is deposited by ALD; PDA is performed by rapid thermal annealing (RTA) in N2 at 900°C for 1 min and PMA in forming gas for 10 and 40 min. X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements data are studied in addition to capacitance-voltage (C-V) and current-voltage (I-V) characteristics for the fabricated Pd/Al2O3/SiC capacitors. Conduction mechanism contributing to the gate leakage current is extracted for the entire range of gate electric field.

Findings

RTA forms aluminum silicide at the interface causing an increase in the density of the interface states and gate leakage current for devices with an annealed film, when compared with an as-deposited film. One order improvement in leakage current has been observed for the devices with RTA, after subjecting to PMA for 40 min, compared with those devices for which PMA was carried out for 10 min. Whereas, no improvement in leakage current has been observed for the devices on as-deposited film, even after subjecting to PMA for 40 min. Conduction mechanisms contributing to gate leakage current are extracted for the investigated Al2O3/SiC capacitors and are found to be trapfilled limit process at low-field regions; trapassisted tunneling in the mid-field regions and Fowler–Nordheim (FN) tunneling are dominating in high-field regions.

Originality/value

The effect of PDA and PMA on the structural and electrical characteristics of Pd/Al2O3/SiC capacitors suitable for flash memory applications is investigated in this paper.

Details

Microelectronics International, vol. 35 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 29 April 2014

Bongani C. Mabuza and Saurabh Sinha

The purpose of this paper was to present the results of the three types of FG transistors that were investigated. The reliability issues of oxide thickness due to programming…

Abstract

Purpose

The purpose of this paper was to present the results of the three types of FG transistors that were investigated. The reliability issues of oxide thickness due to programming, fabrication defects and process variation may cause leakage currents and thus charge retention failure in the floating gate (FG).

Design/methodology/approach

The tunnelling and electron injection methods were applied to program FG devices of different lengths (180 and 350 nm) and coupling capacitor sizes. The drain current and threshold voltage changes were determined for both gate and drain voltage sweep. The devices were fabricated using IBM 130 nm process technology.

Findings

Current leakages are increasing with device scaling and reducing the charge retention time. During programming, charge traps may occur in the oxide and prevent further programming. Thus, the dominant factors are the reliability of oxide thickness to avoid charge traps and prevent current/charge leakages in the FG devices. The capacitive coupling (between the tunnelling and electron injection capacitors) may contribute to other reliability issues if not properly considered.

Originality/value

Although the results have raised further research questions, as revealed by certain reliability issues, they have shown that the use of FGs with nanoscale technology is promising and may be suitable for memory and switching applications.

Details

Microelectronics International, vol. 31 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 April 1991

J.B. Johnson, S.H. Voldman and T.D. Linton

Challenges to a robust and accurate implementation of electric‐field‐enhanccd thermal‐generation mechanisms in a drift‐diffusion‐based semiconductor‐device simulation code are…

Abstract

Challenges to a robust and accurate implementation of electric‐field‐enhanccd thermal‐generation mechanisms in a drift‐diffusion‐based semiconductor‐device simulation code are discussed and solutions proposed. The implementation of the physical models and associated numerical methods is applied to the simulation of leakage currents in trench‐DRAM cells.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 10 no. 4
Type: Research Article
ISSN: 0332-1649

Article
Publication date: 1 October 2018

Prashant Singh, Rajesh Kumar Jha, Rajat Kumar Singh and B.R. Singh

Development of (1T-type) ferroelectric random access memory (FeRAM) has most actively progressed since 1995 and motivated by the physical limits and technological drawbacks of the…

Abstract

Purpose

Development of (1T-type) ferroelectric random access memory (FeRAM) has most actively progressed since 1995 and motivated by the physical limits and technological drawbacks of the flash memory. 1T-type FeRAM implements ferroelectric layer at the field effect transistor (FET) gate. During the course of the investigation, it was very difficult to form a thermodynamically stable ferroelectric-semiconductor interface at the FET gate, leading to the introduction of one insulating buffer layer between the ferroelectric and the silicon substrate to overcome this problem. In this study, Al2O3 a high-k buffer layer deposited by plasma enhanced atomic layer deposition (PEALD) is sandwiched between the ferroelectric layer and silicon substrate.

Design/methodology/approach

Ferroelectric/high-k gate stack were fabricated on the silicon substrate and pt electrode. Structural characteristics of the ferroelectric (PZT) and high-k (Al2O3) thin film deposited by RF sputtering and PEALD, respectively, were optimized and investigated for different process parameters. Metal/PZT/Metal, Metal/PZT/Silicon, Metal/PZT/Al2O3/Silicon structures were fabricated and electrically characterized to obtain the memory window, leakage current, hysteresis, PUND, endurance and breakdown characteristics.

Findings

XRD pattern shows the ferroelectric perovskite thin Pb[Zr0.35Ti0.65]O3 film with (101) tetragonal orientation deposited by sputtering and PEALD Al2O3 with (312) orientation showing amorphous nature. Multiple angle analysis shows that the refractive index of PZT varies from 2.248 to 2.569, and PEALD Al2O3 varies from 1.6560 to 1.6957 with post-deposition annealing temperature. Increase in memory window from 2.3 to 8.4 V for the Metal-Ferroelectric-Silicon (MFS) and Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure has been observed at the annealing temperature of 500°C. MFIS structure with 10 nm buffer layer shows excellent endurance of 3 × 109 read-write cycles and the breakdown voltage of 33 V.

Originality/value

This paper shows the feature, principle and improvement in the electrical properties of the fabricated gate stack for 1T-type nonvolatile FeFET. The insulating buffer layer sandwiched between ferroelectric and silicon substrate acts as a barrier to ferroelectric–silicon interdiffusion improves the leakage current, memory window, endurance and breakdown voltage. This is perhaps the first time that the combination of sputtered PZT on the PEALD Al2O3 layer is being reported.

Details

Microelectronics International, vol. 35 no. 4
Type: Research Article
ISSN: 1356-5362

Keywords

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