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The purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model.

The design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy.

The proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. I_on/I_ambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs.

The modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

This paper aims to investigate the influence of composite solder joint preparation on the thermal properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the mechanical strength of the soldered joint.

Reinforced composite solder joints with the addition of titanium oxide nanopowder (TiO₂) were prepared. The reference alloy was Sn99Ag0.3Cu0.7. Reinforced joints differed in the weight percentage of TiO₂, ranging from 0.125 to 1.0 Wt.%. Two types of components were used for the tests. The resistor in the 0805 package was used for mechanical strength tests, where the component was soldered to the FR4 substrate. For thermal parameters measurements, a power element MOSFET in a TO-263 package was used, which was soldered to a metal core printed circuit board (PCB) substrate. Components were soldered in batch IR oven.

Shear tests showed that the addition of titanium oxide does not significantly increase the resistance of the solder joint to mechanical damage. Titanium oxide addition was shown to not considerably influence the soldered joint’s mechanical strength compared to reference samples when soldered in batch ovens. Thermal resistance R_thj-a of MOSFETs depends on TiO₂ concentration in the composite solder joint reaching the minimum R_thj at 0.25 Wt.% of TiO₂.

Mechanical strength: TiO₂ reinforcement shows minimal impact on mechanical strength, suggesting altered liquidus temperature and microstructure, requiring further investigation. Thermal performance: thermal parameters vary with TiO₂ concentration, with optimal performance at 0.25 Wt.%. Experimental validation is crucial for practical application. Experimental confirmation: validation of optimal concentrations is essential for accurate assessment and real-world application. Soldering method influence: batch oven soldering may affect mechanical strength, necessitating exploration of alternative methods. Thermal vs mechanical enhancement: while TiO₂ does not notably enhance mechanical strength, it improves thermal properties, highlighting the need for balanced design in power semiconductor assembly.

Incorporating TiO₂ enhances thermal properties in power semiconductor assembly. Optimal concentration balancing thermal performance and mechanical strength must be determined experimentally. Batch oven soldering may influence mechanical strength, requiring evaluation of alternative techniques. TiO₂ composite solder joints offer promise in power electronics for efficient heat dissipation. Microstructural analysis can optimize solder joint design and performance. Rigorous quality control during soldering ensures consistent thermal performance and mitigates negative effects on mechanical strength.

The integration of TiO₂ reinforcement in solder joints impacts thermal properties crucial for power semiconductor assembly. However, its influence on mechanical strength is limited, potentially affecting product reliability. Understanding these effects necessitates collaborative efforts between researchers and industry stakeholders to develop robust soldering techniques. Ensuring optimal TiO₂ concentration through experimental validation is essential to maintain product integrity and safety standards. Additionally, dissemination of research findings and best practices can empower manufacturers to make informed decisions, fostering innovation and sustainability in electronic manufacturing processes. Ultimately, addressing these social implications promotes technological advancement while prioritizing consumer trust and product quality in the electronics industry.

The research shows the importance of the soldering technology used to assemble MOSFET devices.

This paper presents the outcomes of the international project “Protecting Landscape Heritage: a requalification project as an instrument for the re-birth of Quang Tri Old Citadel in Vietnam”, achieved with scientific cooperation between the Università Politecnica delle Marche (Italy) and Hue University of Sciences (Vietnam) funded by the Italian Ministry of Foreign Affairs and International Cooperation and Ministry of Science and Technology of Vietnam. The research focuses on the Quang Tri Citadel, founded in 1809 and now in an advanced state of degradation.

For the purpose of rehabilitation, the wide multidisciplinary project first examined the historical context of the military model, the architectural aspects of the structure, the characterization of the existing materials, the degradation levels of different parts, and, finally, a proposal of the suggested interventions.

The original structure and geometry were extrapolated and studied. Building materials were produced with nearby raw materials. Firing temperatures of bricks ranged from 800 to 1,000 °C, hydraulic lime was supposed the binder of the mortar with a calcination temperature lower than 1,000 °C. Damage assessment was provided and after these analyses a requalification project was proposed so the cultural heritage can play a role for the future in the dialog between different cultures.

The requalification project achieved by an integrated analytical approach defines aspects in relation to the restoration of the structures, enabling compliance with the geometry, techniques, building materials used in the original construction and allowing its guardianship and management to align with the historical context of the architectural heritage.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

Surface acoustic wave (SAW) sensors have attracted great attention worldwide for a variety of applications in measuring physical, chemical and biological parameters. However, stability has been one of the key issues which have limited their effective commercial applications. To fully understand this challenge of operation stability, this paper aims to systematically review mechanisms, stability issues and future challenges of SAW sensors for various applications.

This review paper starts with different types of SAWs, advantages and disadvantages of different types of SAW sensors and then the stability issues of SAW sensors. Subsequently, recent efforts made by researchers for improving working stability of SAW sensors are reviewed. Finally, it discusses the existing challenges and future prospects of SAW sensors in the rapidly growing Internet of Things-enabled application market.

A large number of scientific articles related to SAW technologies were found, and a number of opportunities for future researchers were identified. Over the past 20 years, SAW-related research has gained a growing interest of researchers. SAW sensors have attracted more and more researchers worldwide over the years, but the research topics of SAW sensor stability only own an extremely poor percentage in the total researc topics of SAWs or SAW sensors.

Although SAW sensors have been attracting researchers worldwide for decades, researchers mainly focused on the new materials and design strategies for SAW sensors to achieve good sensitivity and selectivity, and little work can be found on the stability issues of SAW sensors, which are so important for SAW sensor industries and one of the key factors to be mature products. Therefore, this paper systematically reviewed the SAW sensors from their fundamental mechanisms to stability issues and indicated their future challenges for various applications.

Field-effect transistor (FET) has excellent electronic properties and inherent signal amplification, and with the development of nanomaterials technology, FET biosensors with nanomaterials as channels play an important role in the field of heavy metal ion detection. This paper aims to review the research progress of silicon nanowire, graphene and carbon nanotube field-effect tube biosensors for heavy metal ion detection, so as to provide technical support and practical experience for the application and promotion of FET.

The article introduces the structure and principle of three kinds of FET with three kinds of nanomaterials, namely, silicon nanowires, graphene and carbon nanotubes, as the channels, and lists examples of the detection of common heavy metal ions by the three kinds of FET sensors in recent years. The article focuses on the advantages and disadvantages of the three sensors, puts forward measures to improve the performance of the FET and looks forward to its future development direction.

Compared with conventional instrumental analytical methods, FETs prepared using nanomaterials as channels have the advantages of fast response speed, high sensitivity and good selectivity, among which the diversified processing methods of graphene, the multi-heavy metal ions detection of silicon nanowires and the very low detection limit and wider detection range of carbon nanotubes have made them one of the most promising detection tools in the field of heavy metal ions detection. Of course, through in-depth analysis, this type of sensor has certain limitations, such as high cost and strict process requirements, which are yet to be solved.

This paper elaborates on the detection principle and classification of field-effect tube, investigates and researches the application status of three kinds of FET biosensors in the detection of common heavy metal ions. By comparing the advantages and disadvantages of each of the three sensors in practical applications, the paper focuses on the feasibility of improvement measures, looks forward to the development trend in the field of heavy metal detection and ultimately promotes the application of field-effect tube development technology to continue to progress, so that its performance continues to improve and the application field is constantly expanding.

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

The purpose of this research is to study the performance of piezoresistive pressure sensors using polysilicon as the piezoresistive material, which is typically used to measure pressure in high-temperature environments.

The performance of this sensor is enhanced by studying the influence of multi-turn configuration at which the piezoresistors are arranged. Different configurations are studied and compared by laying down their analytical solution.

The validation of analytical results is accomplished through finite element analysis using the software COMSOL Multiphysics. The best configuration, which uses a partial triple-turn configuration, was able to achieve a sensitivity of 116.00 mV/V/MPa over a simulated pressure range of 0 to 500 KPa.

The literature shows the study of single-turn and double-turn meander-shaped configuration of micro-electromechanical systems piezoresistive pressure sensor but multi-turn meander-shaped configuration using a square silicon diaphragm has not been reported. Its study has reflected promising results than its counterparts based on key performance parameters such as sensitivity and linearity and are more effective to be used for automotive, aviation, biomedical and consumer electronics applications.

This study aims to provide a microfluidic blood glucose sensing platform based on integrated interdigitated electrode arrays (IDEAs) on a flexible quartz glass substrate, adhering closely to pertinent electrochemical characterizations.

Sensors are the key elements of the modern electronics era through which all the possible physical quantities can be detected and converted into their equivalent electrical form and processed further. But to make the sensing environment better, various types of innovative architectures are being developed nowadays and among them interdigitated electrodes are quite remarkable in terms of their sensing capability. They are a well-qualified candidate in the field of gas sensing and biosensing, but even their sensitivities are getting saturated due to their physical dimensions. Most of the thin film IDEAs fabricated by conventional optical lithographic techniques do not possess a high surface-to-volume ratio to detect the target specified and that reduces their sensitivity factor. In this context, a classic conductive carbon-based highly sensitive three dimensional (3D) IDEA-enabled biosensing system has been conceived on a transparent and flexible substrate to measure the amount of glucose concentration present in human blood. 3D IDEA possesses a way better capacitive sensing behavior compared to conventional thin film microcapacitive electrodes. To transmit the target biological analyte sample property for the detection purpose to the interdigitated array-based sensing platform, the design of a microfluidic channel is initiated on the same substrate. The complex 3D Inter Digital array structure improves the overall capacitance of the entire sensing platform and the reactive surface area as well. The manufactured integrated device displays a decent value of sensitivity in the order of 5.6 µA mM⁻¹ cm⁻².

Development of a low-cost array-based integrated and highly flexible microfluidic biochip to extract the quantity of glucose present in human blood.

Potential future research opportunities in the realm of integrated miniaturized, low-cost smart biosensing systems may arise from this study.