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This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.

The integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.

Experiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.

The proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.

An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm².

Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.

The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

The purpose of this paper is to develop a model of the inductive link for implantable systems. The model is suitable for a cochlear implant in which a lateral misalignment and distance coil can be up to 16 mm.

The description of the generation of implantable systems' high‐power, such as a cochlear implant, are powered by transcutaneous inductive power links formed by two coils: the first is a printed spiral coil used in the receiver device and the second is a solenoid coil used in the emitter device. Optimizing the power efficiency of the wireless link is imperative to minimize the size of the external energy source, heating dissipation in the tissue, and interference with other devices. The authors have outlined the theoretical foundation of optimal power transmission efficiency in an inductive link, and combined it with semi‐empirical models to predict parasitic components. The power amplifier itself is a class‐E amplifier optimized in both output voltage and efficiency, and bears an excellent tolerance to misalignments.

Two Spice‐based electrical models of the coils are achieved. The technique employed during the work is based on polynomial interpolation of the mutual inductance in which coil misalignments are considered as variables. On the other hand, a voltage regulator is studied and simulated by Cadence Analog Artist in the AMS 0.35 μm CMOS technology.

This paper provides a novel and useful method for transmitting power for an implantable system via an inductive link. The procedure of the authors' design is achieved at 10 MHz and the power transmission efficiency is 35 percent, whatever the longitudinal misalignment (up to 16 mm) between both coils.

The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.

This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.

The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.

All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.

The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.

The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

To solve the above problems and ensure the stability of the ad hoc network node topology in the process of wireless signal transmission, this paper aims to design a robust adaptive sliding film fault-tolerant controller under the nonlinear distortion of signal transmission in an amorphous flat air-to-ground wireless ad hoc network system.

This paper designs a robust adaptive sliding film fault-tolerant controller under the nonlinear distortion of signal transmission in an amorphous flat air-to-ground wireless ad hoc network system.

The simulation results show that the amorphous flat wireless self-organizing network system has good nonlinear distortion fault-tolerant correction ability under the feedback control of the designed controller, and the system has the asymptotically stable convergence ability; the test results show: the node topology of the self-organizing network structural stability is significantly improved, which provides a foundation for the subsequent realization of long-distance transmission of ad hoc network nodes.

Because of the chosen research approach, the research results may lack generalizability. Therefore, researchers are encouraged to test the proposed propositions further.

The controller can extract the fault information caused by nonlinear distortion in the wireless signal transmission process, and at the same time, its feedback matrix K can gradually converge the generated wireless signal error to zero, to realize the stable transmission of the wireless signal.

This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.

A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P_−1dB), power dissipation and reduction of switching quad C_gs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.

A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P_−1dB in 0.18‐μm CMOS technology.

The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.

The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.

In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.

The paper aims to design of dual-mode boost converter with integrated low-voltage control circuit is introduced in this paper. The paper aims to discuss these issues.

The converter is operated either with LC filter or with charge pump circuit by the switch control. The control stage with error amplifier, comparator, and oscillator is designed with the supply voltage of 3.3 V and the operating frequency of 5.5 MHz. The compensator circuit exploits a pole compensation for a stable operation.

The simulation test in 0.35 μm CMOS process shows that the charge pump regulator and DC-DC boost converter are accurately controlled with the variation of number of stages and duty ratio. The output-voltage is obtained to be 6-15 V within the ripple ratio of 5 percent. Maximum power consumption is about 0.65 W.

This dual-mode is useful in the converter with a wide load-current variation. The advantage of the dual-mode converter is that it can be used in either high or low load current with a simple switch control. Furthermore, in charge pump regulator, there is no degradation of output voltage because of the feedback control circuit.

The purpose of this paper is to present a fully integrated power converter. A stacked spiral inductor is applied in a voltage‐mode CMOS DC‐DC converter for the chip miniaturization and low‐power operation.

The three‐layer spiral inductor is simulated with an equivalent circuit and applied to the DC‐DC converter. The DC‐DC buck converter has been fabricated with a standard 0.35 μm CMOS process. The power converter is measured in both experiment and simulation in terms of frequency and electrical characteristics.

Experimental results show that the converter with the stacked spiral inductor operates properly with the inductance of 7.6 nH and mW power range. The measured inductance of the stacked spiral inductor is found to be almost half of the circuit designed value because of the parasitic resistances and capacitances in the spiral inductor.

This paper first introduces the application of the integrated stacked spiral inductor in DC‐DC buck converter for display driver circuit, which requires a low‐power operation. It also shows the fully integrated DC‐DC converter for chip miniaturization.

THE basic autostabiliser system requirements are that the aircraft control surface position be controlled by signals derived from the aircraft's angular velocities. The gearing between these two quantities is required to be inversely proportional to a pressure derived signal, which may be cither dynamic pressure (at less than Mach 0·95) or static pressure (at greater than Mach 0·95), and limits are imposed on the range of this gain scheduling.

The paper aims to present a simple rail‐to‐rail CMOS voltage follower.

The circuit is developed based on a complementary source follower with a common‐source output stage. The circuit is designed using a 0.13 μm CMOS technology, and operates under the supply voltage of 1.5 V. HSPICE is used to verify the circuit performance.

The simulations show output voltage swing of ±0.6 V (300 Ω load) with the total harmonic distortion of 0.55 per cent at the operating frequency of 3 MHz. The bandwidth and power dissipation are 657 MHz and 405 μW, respectively.

A simple rail‐to‐rail CMOS voltage follower is presented.