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The purpose of this paper is to develop a familiarity analysis of resistive-capacitive (RC) network active circuit operating with unfamiliar low-pass (LP) type negative group delay (NGD) behavior. The design method of NGD circuit is validated by simulation with commercial tool and experimental measurement.

The present research work methodology is structured in three main parts. The familiarity theory of RC-network LP-NGD circuit is developed. The LP-NGD circuit parameters are expressed in function of the targeted time-advance. Then, the feasibility study is based on the theory, simulation and measurement result comparisons.

The RC-network based LP-NGD proof of concept is validated with −1 and −0.5 ms targeted time-advances after design, simulation, test and characterized. The LP-NGD circuit unity gain prototype presents NGD cut-off frequencies of about 269 and 569 Hz for the targeted time-advances, −1 and −0.5 ms, respectively. Bi-exponential and arbitrary waveform signals were tested to verify the targeted time-advance.

The performance of the unfamiliar LP-NGD topology developed in the present study is limited by the parasitic elements of constituting lumped components.

The NGD circuit enables to naturally reduce the undesired delay effect from the electronic and communication systems. The NGD circuit can be exploited to reduce the delay induced by electronic devices and system.

As social impacts of the NGD circuit application, the NGD function is one of prominent solutions to improve the technology performances of future electronic device in term of communication aspect and the transportation system.

The originality of the paper concerns the theoretical approach of the RC-network parameters in function of the targeted time-advance and the input signal bandwidth. In addition, the experimental results are also particularly original.

The purpose of this paper is to design and construct an amplitude shift keying (ASK) modulator, which, using the digital binary modulating signal, controls a floating memristor emulator (MR) internally without the need for additional control circuits to achieve the ASK modulated wave.

A binary digital unipolar signal to be modulated is converted by a pre-processor circuit into a suitable bipolar modulating direct current (DC) signal for the control of the MR state, using current conveyors the carrier signal’s amplitude is varied with the change in the memristance of the floating MR. A high pass filter is then used to remove the DC control signal (modulating signal) leaving only the modulated carrier signal.

The results from the experiment and simulation are in agreement showed that the MR can be switched between two states and that a change in the carrier signals amplitude can be achieved by using an MR. Thus, showing that the circuit behavior is in line with the proposed theory and validating the said theory.

In this paper, the binary signal to be modulated is modified into a suitable control signal for the MR, thus the MR relies on the internal operation of the modulator circuit for the control of its memristance. An ASK modulation can then be achieved using a floating memristor without the need for additional circuits or signals to control its memristance.

This paper aims to present the design development and measurement of two aerodynamic slotted X-bands back-to-back planer substrate-integrated rectangular waveguide (SIRWG/SIW) to Microstrip (MS) line transition for satellite and RADAR applications. It facilitates the realization of nonplanar (waveguide-based) circuits into planar form for easy integration with other planar (microstrip) devices, circuits and systems. This paper describes the design of a SIW to microstrip transition. The transition is broadband covering the frequency range of 8–12 GHz. The design and interconnection of microwave components like filters, power dividers, resonators, satellite dishes, sensors, transmitters and transponders are further aided by these transitions. A common planar interconnect is designed with better reflection coefficient/return loss (RL) (S₁₁/S₂₂ ≤ 10 dB), transmission coefficient/insertion loss (IL) (S₁₂/S₂₁: 0–3.0 dB) and ultra-wideband bandwidth on low profile FR-4 substrate for X-band and Ku-band functioning to interconnect modern era MIC/MMIC circuits, components and devices.

Two series of metal via (6 via/row) have been used so that all surface current and electric field vectors are confined within the metallic via-wall in SIW length. Introduced aerodynamic slots in tapered portions achieve excellent impedance matching and tapered junctions with SIW are mitered for fine tuning to achieve minimum reflections and improved transmissions at X-band center frequency.

Using this method, the measured IL and RLs are found in concord with simulated results in full X-band (8.22–12.4 GHz). RLC T-equivalent and p-equivalent electrical circuits of the proposed design are presented at the end.

The measurement of the prototype has been carried out by an available low-cost X-band microwave bench and with a Keysight E4416A power meter in the microwave laboratory.

The transition is fabricated on FR-4 substrate with compact size 14 mm × 21.35 mm × 1.6 mm and hence economical with IL lie within limits 0.6–1 dB and RL is lower than −10 dB in bandwidth 7.05–17.10 GHz. Because of such outstanding fractional bandwidth (FBW: 100.5%), the transition could also be useful for Ku-band with IL close to 1.6 dB.

When rotor and stator teeth are close, the connecting air gap flux tube's cross-sectional area exceeds the tooth overlap area. This flux fringing effect is disregarded in the air gap permeance calculation of single-slice magnetic equivalent circuits (MECs) of electric motors with skewed rotors. This paper aims to extend an air gap permeance calculation method incorporating flux fringing for unskewed rotors to skewed and radially eccentric rotors.

Assuming axial independence, the unskewed air gap permeance is rotated according to the skew and integrated along the axial dimension, resulting in a first method. The integral is approximated analytically, resulting in a second method. Results are compared to a commonly used reference method and validated using a non-linear finite element method (FEM) simulation.

The proposed methods provide better alignment with the FEM validation compared to the reference method for skewed rotors and common rotor eccentricity, i.e. below 50% of the air gap length. The analytical method is shown to be competitive with the reference method regarding computational time cost.

Two novel air gap permeance methods are proposed for single-slice MECs with skewed rotors. Their characteristics are discussed and validated.

The purpose of this paper is to gain a better understanding on how metasurfaces behave, in terms of currents in each unit cell. A better knowledge of their behavior could lead to an ad-hoc design for specific applications.

The methodology used is both theoretical and numerical; it is based on circuit theory and on an optimization procedure.

The results show that when the knowledge of the current in each unit cell of a metasurface is needed, the most common approximations currently used are often not accurate. Furthermore, a procedure for the termination of a metasurface, with application-driven goals, is given.

This paper investigates the distribution of the currents in a 2D metamaterial realized with magnetically coupled resonant coils. Different models for the analysis of these structures are illustrated, and the effects of the approximations they introduce on the current values are shown and discussed. Furthermore, proper terminations of the resonators on the boundaries have been investigated by implementing a numerical optimization procedure with the purpose of achieving a uniform distribution of the resonator currents. The results show that the behavior of a metasurface (in terms of currents in each single resonator) depends on different properties; as a consequence, their design is not a trivial task and is dependent on the specific applications they are designed for. A design strategy, with lumped impedance termination, is here proposed.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

This paper aims to present a low-cost, edge-fed, windmill-shaped, notch-band eliminator, circular monopole antenna which is practically loaded with a complementary split ring resonator (CSRR) in the middle of the radiating conductor and also uses a partial ground to obtain wide-band performance.

To compensate for the reduced value of gain and reflection coefficient because of the full (complete) ground plane at the bottom of the substrate, the antenna is further loaded with a partial ground and a CSRR. The reduction in the length of ground near the feed line improves the impedance bandwidth, and introduced CSRR results in improved gain with an additional resonance spike. This results in a peak gain 3.895dBi at the designed frequency 2.45 GHz. The extending of three arms in the circular patch not only led to an increase of peak gain by 4.044dBi but also eliminated the notch band and improved the fractional bandwidth 1.65–2.92 GHz.

The work reports a –10dB bandwidth from 1.63 GHz to 2.91 GHz, which covers traditional coverage applications and new specific uses applications such as narrow LTE bands for future internet of things (NB-IoT) machine-to-machine communications 1.8/1.9/2.1/2.3/2.5/2.6 GHz, industry, automation and business-critical cases (2.1/2.3/2.6 GHz), industrial, society and medical applications such as Wi-MAX (3.5 GHz), Wi-Fi3 (2.45 GHz), GSM (1.9 GHz), public safety band, Bluetooth (2.40–2.485 GHz), Zigbee (2.40–2.48Ghz), industrial scientific medical (ISM) band (2.4–2.5 GHz), WCDMA (1.9, 2.1 GHz), 3 G (2.1 GHz), 4 G LTE (2.1–2.5 GHz) and other personal communication services applications. The estimated RLC electrical equivalent circuit is also presented at the end.

Because of full coverage of Bluetooth, Zigbee, WiFi3 and ISM band, the proposed fabricated antenna is suitable for low power, low data rate and wireless/wired short-range IoT-enabled medical applications.

The antenna is fabricated on a piece (66.4 mm × 66.4 mm × 1.6 mm) of low-cost low profile FR-4 epoxy substrate (0.54 λ_g × 0.54 λ_g) with a dielectric constant of 4.4, a loss tangent of 0.02 and a thickness of 1.6 mm. The antenna reflection coefficient, impedance and VSWR are tested on the Keysight technology (N9917A) vector network analyzer, and the radiation pattern is measured in an anechoic chamber.

Conventional isolated dc–dc converters offer an efficient solution for performing voltage conversion with a large improved voltage gain. However, the small-signal analysis of these converters shows that a right-half-plane (RHP) zero appears in their control-to-output transfer function, exhibiting a nonminimum-phase stability. This RHP zero can limit the frequency response and dynamic specifications of the converters; therefore, the output voltage response is sluggish. To overcome these problems, the purpose of this study is to analyze, model and design a new isolated forward single-ended primary-inductor converter (IFSEPIC) through RHP zero alleviation.

At first, the normal operation of the suggested IFSEPIC is studied. Then, its average model and control-to-output transfer function are derived. Based on the obtained model and Routh–Hurwitz criterion, the components are suitably designed for the proposed IFSEPIC, such that the derived dynamic model can eliminate the RHP zero.

The advantages of the proposed IFSEPIC can be summarized as: This converter can provide conditions to achieve fast dynamic behavior and minimum-phase stability, owing to the RHP zero cancellation; with respect to conventional isolated converters, a larger gain can be realized using the proposed topology; thus, it is possible to attain a smaller operating duty cycle; for conventional isolated converters, transformer core saturation is a major concern, owing to a large magnetizing current. However, the average value of the magnetizing current becomes zero for the proposed IFSEPIC, thereby avoiding core saturation, particularly at high frequencies; and the input current of the proposed converter is continuous, reducing input current ripple.

The key benefits of the proposed IFSEPIC are shown via comparisons. To validate the design method and theoretical findings, a practical implementation is presented.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

This study investigates Rokkan's research programme in the light of the differences between case- and variables-based methodologies. Three phases of the research process are distinguished. Studying the way Rokkan actually proceeded in the research within his Europe project, we find that he follows the protocols of case-methodologies such as grounded theory. In the second phase of the research process, however, he constructs variables-based models as tools for his macro-historical comparisons. To get to variables from the sensitizing concepts coded in the first phase, Rokkan defines his variables as close to cases as possible: variables as nominal level typologies, types as variable values. He thus faces two interrelated dilemmas. First, a philosophy of science dissonance: he legitimates his research only with reference to a variable-methodology, while his research is thoroughly case based. Second, a paradox of double coding: using variable-based models in the second phase, the status of the knowledge available in the first phase memos is degraded. Rokkan cannot decide between the two main solutions to these dilemmas: The first solution is to discard his heterogeneous data, instead working only with homogeneous data that opens up to more consistently variables-oriented research. The second solution is to replace the notion of variables/variable values with typology/types, thereby returning to cases, pursuing comparative case reconstructions in the third phase of research. The study concludes in favour of the second solution.