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Highly accelerated tests, while capable of producing failures in short test durations, can cause significant damage and failure as a result of damage mechanisms and/or material behaviour not present in the actual use of electronic product. This is particularly true for surface mount solder attachments. The results of low‐acceleration reliability tests for the solder attachments of ball grid arrays (BGAs) and column grid arrays (CGAs) are reported in this paper. The tests were designed to mimic the thermal conditions of the use environment of the product, including internal power dissipation within the grid array components, as closely as practically possible. The test acceleration comes from two measures taken: (1) controlled reduced dwell times at the cyclic temperature extremes, thus allowing a higher cyclic frequency, and (2) a controlled increased CTE‐mismatch between the components and the test circuit board by an increase in the coefficient of thermal expansion (CTE) of the test circuit boards relative to the product cirucit boards. Control test vehicles with product‐like circuit board construction were also utilised. The results from the different test vehicle configurations are correlated and utilised to estimate the reliability of the product in the field.

By the use of ceramic ball grid array connections, the number of I/Os can be increased substantially in comparison with PGA (pin grid array) while maintaining an unchanged module size. In most cases, this also signifies a higher packing density and thus a higher power density, which must be dissipated as occurring heat. The fact that the dissipation of heat can also be improved considerably by the use of modules with CBGA (ceramic ball grid array) connections instead of PGA connections is demonstrated on a simulation model. Moreover, the use of chip carriers made of different ceramics (LTCC or Al₂O₃) has a substantial influence on the possible heat dissipation (LTCC= low temperature cofired ceramic).

A no‐clean mass reflow process for 396‐pin, 324‐pin and 225‐pin over moulded plastic pad array carriers (OMPACs) or plastic ball grid array (BGA) is presented. Emphasis is placed on the OMPAC assembly parameters such as the design, material and process of the packages and printed circuit board (PCB), solder paste, stencil design, printing technology, pick and place, mass re‐flow and inspection. Furthermore, cross‐sections and the ‘popcorn’ effect of the OMPAC assembly are provided and discussed.

The increased use recently of area‐array technology in electronic packaging has similarly increased the importance of predicting the thermal distribution of area‐array solder interconnection. As the interconnection technology for flip chip package is getting finer and smaller, it is extremely difficult to obtain the accurate values of thermal stresses by direct experimental measurements. Different types of solder bumps used for interconnection would also influence the thermal distribution within the package. Because the solder balls are too small for direct measurement of their stresses, finite element method (FEM) was used for obtaining the stresses instead.

This paper will discuss the results of the thermal stress distribution using numerical method via ABAQUS software. The variation of the thermal stress distribution with the temperature gradient model was evaluated to study the effects of the different material thermal conductivity of solder bumps used. A detailed 2D finite element model was constructed to perform 2D plain strain elastoplastic analysis to predict areas of high stress.

It is found that thermal distribution of solder bumps starts to propagate from the top region to the bottom region of the solder balls. Other than that, thermal stress effect increases in parallel with the increasing of the temperature. The simulation results shows that leaded solder balls, SnPb have higher maximum thermal stress level compared to lead‐free SAC solder balls.

The paper describes combination of stress with thermal loading correlation on a flip chip model. The work also shows how the different thermal conductivity on solder balls influences the thermal induced stress on the flip chip package.

The objective of this paper is to point out the limitations and ròles of DNP (distance to neutral point) on predicting the solder‐joint thermal‐fatigue life of area‐array assemblies.

This paper gives a bibliographical review of the finite element methods (FEMs) applied to the analysis of ceramics and glass materials. The bibliography at the end of the paper contains references to papers, conference proceedings and theses/dissertations on the subject that were published between 1977‐1998. The following topics are included: ceramics – material and mechanical properties in general, ceramic coatings and joining problems, ceramic composites, ferrites, piezoceramics, ceramic tools and machining, material processing simulations, fracture mechanics and damage, applications of ceramic/composites in engineering; glass – material and mechanical properties in general, glass fiber composites, material processing simulations, fracture mechanics and damage, and applications of glasses in engineering.

The purpose of this paper is to develop a cost effective ball grid array (BGA) workcell for solder ball attachment.

This paper presents the construction of a low‐cost high‐efficiency automatic ball attachment workcell. In fact, it is an economical means of simultaneous placement of all solder balls on BGA substrates containing multiple BGA units as well as singulated substrates. Common industry problems such as the effect of static charges, the solder ball oxidation, the missing ball, the extra ball, the ball alignment, the deformed ball and, etc. will be addressed and critical issues affecting yield will also be discussed in this paper.

BGA is a popular integrated circuit packaging that is often applied in laptop computers and other handheld electronic devices for the provision of a high‐connection count in a relatively small area. However, the cost of a market available BGA solder ball attachment workcell is very expensive and the flexibility in fitting various customized process is usually low.

The developed workcell cost is about half of the market available machines with similar specifications; the yield achieved is within three sigma confidence interval with competitive output rate. The maintenance and troubleshooting are easy since the machine was developed by the in‐house engineering team.

BGAs are a new type of surface mountable component. Successful industrial implementation of BGA assembly on electronic boards needs specific studies, evaluations and qualification. The methodology used in Bull is presented, along with an analysis of the different BGA types. Implementation and qualification results are provided.

A simple analysis method was developed to determine the fatigue life of a ceramic ball grid array (CBGA) solder joint when exposed to thermal environments. The solder joint consists of a 90Pb/10Sn solder ball with eutectic SnPb solder on both top and bottom of the ball. A closed‐form solution, based on the calculation of the equilibrium of the displacements within the electronic package assembly, was first derived in order to calculate the solder joint strains during temperature cycling. In the calculation, an iteration technique was used to obtain a convergent solution for the solder strains, and the elastic material properties were used for all the electronic package assembly components except for the solder materials. A fatigue life prediction model was established.

This paper describes some recent innovations in design, process and materials in printed circuit laminate technology, which can lead to significant paradigm shifts in the design and application of electronic products. The traditional roles for printed circuit cards and boards have been to provide wiring interconnection capacity, and a robust mechanical structure for the more delicate and costly chips and modules. The advent of surface mount technology eliminated the need for plated‐through holes as anchors for pinned components. The proliferation of light, high performance, multifunction electronic products will lead to light weight, small, low profile printed circuit assemblies. Adding a redistribution layer to the traditional card surface allows flip‐chip‐on‐board and MCM‐L packages as a low‐cost alternative to traditional high density MCM packages, particularly in applications where size, shape and weight are as important as density and performance. Concurrent with the deliberate evolution of traditional printed circuit technology, some important new materials and process innovations have brought about a new generation of laminate capabilities that are particularly important for the future high I/O requirements predicted for the second part of this decade.