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These implementations not only generate excessive voltage levels to enhance the quality of power but also include a detailed investigating of the various modulation methods and control schemes for multilevel inverter (MLI) topologies. Reduced harmonic modulation technology is used to produce 11-level output voltage with the production of renewable energy applications. The simulation is done in the MATLAB/Simulink for 11-level symmetric MLI and is correlated with the conventional inverter design.

This paper is focused on investigating the different types of asymmetric, symmetric and hybrid topologies and control methods used for the modular multilevel inverter (MMI) operation. Classical MLI configurations are affected by performance issues such as poor power quality, uneconomic structure and low efficiency.

The variations in both carrier and reference signals and their performance are analyzed for the proposed inverter topologies. The simulation result compares unipolar and bipolar pulse-width modulation (PWM) techniques with total harmonic distortion (THD) results. The solar-fed 11-level MMI is controlled using various modulation strategies, which are connected to marine emergency lighting loads. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by using SPARTAN 3A field programmable gate array (FPGA) board and the least harmonics are obtained by improving the power quality.

The simulation result compares unipolar and bipolar PWM techniques with THD results. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by a SPARTAN 3A field programmable gate array (FPGA) board, and the power quality is improved to achieve the lowest harmonics possible.

To improve the voltage quality in AC adjustable high-power-speed-drive applications, the purpose of the paper is to provide a large number of output levels without increasing the number of commutation cells in the three-phase, n-cells flying capacitor voltage source asymmetric Multilevel Inverter (MI). The concept is based on the selection of different ratios between the breakdown voltages of two successive power devices. The new mathematical model is developed under various ratios, allows a thorough investigation of the harmonic distortions, flying capacitor energy storage, flying capacitor voltage balancing controllability and blocking voltage insulated gate bipolar transistor (IGBT) capability.

The asymmetrical design provides a large number of output levels without increasing the number of commutation cells. The important new analytical expression of capacitors voltage distribution is derived and extended to any ratio between the switch breakdown voltages of two successive power devices.

The detailed simulation study of the proposed concept has been carried out using MATLAB/Simulink. The power switches control of the three-phase three-cell MI is assured by new phase-shifted-multi-carrier pulse width modulation. The space vector representation is used to show the regular and irregular step output voltage in the complex plan (α,β).

In the paper, the n cells flying capacitor inverter, which typically operates in the (n + 1) levels mode, was extended to (n + 2), (n + 3) … until 2ⁿ levels with regular or irregular step output voltage. Consequently, the claimed advantages of the asymmetric MI are to improve power quality by reducing harmonic distortions and to reduce the requirement on capacitive energy storage in the circuit.

The purpose of this paper is to present the three phase seven-level Z-source neutral point clamped (NPC) inverter with multicarrier pulse-width modulation (PWM) technique. Despite numerous topologies and modulation methods, there is a dire need of developing PWM techniques that can be deployed in multilevel inverters. These inverters decrease the total harmonic distortion and it has a good performance for various electrical power system applications. The proposed inverter is investigated for its performance by executing it in shoot through and non-shoot through modes.

The purpose is validated through MATLAB/Simulink software platform for implementing the proposed seven-level Z-source NPC inverter outlined with multicarrier based phase disposition technique. The experimental results are verified using SPARTAN 3E FPGA controller with the same control strategy.

The efficiency of the proposed inverter is confirmed in terms of increased and faster conversion in the shoot-through mode. By using PDPWM technique the maximum boost gain is achieved with lower modulation index. High control of DC voltage is obtained with only one DC voltage source and one Z network.

Three phase multilevel inverters are widely used in improving the output voltage quality and reducing the encountered electromagnetic interference in electronic device or circuitry. They are employed in medium and high –power applications to attain increased power ratings while decreasing the switching losses. The performance results shown in this paper will satisfy the above needs of usage in certain applications and less switching losses.

This paper aims to develop a method for a unified model of pulse width modulation (PWM) voltage source inverters (VSI). This generic method, based on a common and easy-to-use carrier-based modulation, allows to generate the exhaustive solution set for a given PWM-VSI.

The use of the generalized inverse theory is developed to express the PWM solution set for the duty cycle. Indeed, the infinite number of PWM solutions is demonstrated. To explore this solution set, the unified model described exhibits degrees of freedom. The admissible margins to set the degree of freedom are highlighted. Some experimental results are presented.

It is demonstrated how the degree of freedom can be directly connected with efficiency indicators such as common mode voltage, inverter linearity and switching losses. The expression of the PWM solution set boundaries is clearly expressed.

Further studies should explore how the degree of freedom can be connected with parameters associated with the current (and not the voltage as described in this paper).

The paper includes implications for the development of a more generic approach for PWM multilevel VSI.

This paper fulfils a mathematical frame to ease the expression of PWM scheme.

The purpose of this paper is to check the Solar Photovoltaic (PV) inverter working condition with modified unipolar switching pulse. The gate pulse for the inverter switches is generated in MATLAB simulation and interfaced with hardware protype. Simulation results can be compared with hardware results.

A considerable amount of research has been done on different Pulse Width Modulation (PWM) techniques. Based on the findings, a modified Unipolar Sinusoidal PWM technique was created with one reference signal and two carrier signals+ (one for the positive half cycle and the other for the negative half cycle) and simulated in the MATLAB/Simulink platform. The prototype inverter module receives the simulated switching pulses via dSPACE DS1104 hardware software interfacing board. The hardware implementation has been done, and the hardware results compared with simulation results for various input voltage levels using resistive load.

This modified switching pulse has dead band and additional hardware setup is not required. 3-phase multi-level inverter output waveform has been achieved with six switches in this method and with low filter values, pure sine wave output can be obtained in simulation. By this method of switching pulse generation and testing, for every modification in switching pulse hardware gate driver is not required. Resulting time consumption and money investment are lower.

Modified Unipolar SPWM pulse generation technique is novel method for solar PV inverter. The switching pulse has been designed and tested in both MATLAB/Simulation and hardware prototype inverter. Hardware and software results are identical. This method of pulse generation and hardware implementation has not been done anywhere before.

This paper presents and investigates a method named M×N‐ary chaotic pulse‐width‐position modulation (CPWPM) which is based on the combination of M‐ary chaotic pulse‐position modulation (CPPM) and N‐ary chaotic pulse‐width modulation (CPWM) in order to provide a better performance in noise‐affected environments as well as improve significantly bit rate.

Analysis of schemes for modulator and demodulator are presented in detail through describing the schemes of the individual methods and their combination. Theoretical evaluation of bit‐error rate (BER) performance in presence of additive white Gaussian noise (AWGN) is provided. Chaotic behavior with tent map in variation of modulation parameters is also investigated. In order to verify the theoretical analyses, numerical simulations are carried out and their results are reported.

Both evaluation and simulation results show that when the number of symbols increases, the bit rate is improved significantly but the BER performance is just slightly worse. This makes M×N‐ary CPWPM become an effective method for chaos‐based digital communication.

Although CPPM, CPWM and M‐ary modulation methods have been described in the literature separately, their combination is presented and investigated for the first time in this paper.

The purpose of this paper is to propose a new method that allows to compare the magnetic pressures of different pulse width modulation (PWM) strategies in a fast and efficient way.

The voltage harmonics are determined using the double Fourier integral. As for current harmonics and waveforms, a new generic model based on the Park transformation and a dq model of the machine was established taking saturation into consideration. The obtained analytical waveforms are then injected into a finite element software to compute magnetic pressures using nodal forces.

The overall proposed method allows to accelerate the calculations and the comparison of different PWM strategies and operating points as an analytical model is used to generate current waveforms.

While the analytical expressions of voltage harmonics are already provided in the literature for the space vector pulse width modulation, they had to be calculated for the discontinuous pulse width modulation. In this paper, the obtained expressions are provided. For current harmonics, different models based on a linear and a nonlinear model of the machine are presented in the referenced papers; however, these models are not generic and are limited to the second range of harmonics (two times the switching frequency). A new generic model is then established and used in this paper after being validated experimentally. And finally, the direct injection of analytical current waveforms in a finite element software to perform any magnetic computation is very efficient.

The purpose of this paper is to clarify the electrical loss of an interior permanent magnet (IPM) motor driven by the pulse‐width modulation (PWM) inverter with various carrier frequencies quantitatively.

An IPM motor driven by the PWM inverter was simulated using the three‐dimensional finite‐element method while changing various carrier frequencies of the PWM inverter. The calculated results are compared with the calculated results differing the number of permanent magnet division.

The eddy current loss in the permanent magnets decreases as the carrier frequency increases. In the case of low‐carrier frequency, the eddy current loss greatly decreases as the number of permanent magnet division increases. However, the effect of the eddy current loss decreases by the number of permanent magnet division as the carrier frequency increases.

The paper describes the electrical loss of an IPM motor driven by the PWM inverter with various carrier frequencies.

Multilevel inverters play a major role in the development of high-power industrial applications. In traditional low-level inverters (e.g. 2-level), the switching frequency is restricted and the harmonic spectrum of the system is hard to meet power requirements. Similarly, high-level inverters consist of a large number of switches, complex modulation techniques and complex hardware architecture, which results in high power loss and a significant amount of harmonic distortion. Furthermore, it is a must to ensure that every switch experiences the same stress of voltage and current. The purpose of this paper is to present an inverter topology with lower conduction and switching losses via reduced number of switches and equal voltage source-sharing technique.

Herein, the authors present a cascaded multilevel inverter having less power switches, a simple modulation technique and an equal voltage source-sharing phenomenon implementation.

The modulation technique becomes more complex when equal voltage source-sharing is to be implemented. In this study, a novel topology for the multilevel inverter with fewer switches, novel modulation technique, equal voltage source-sharing and Inductor-Capacitor-Inductor filter implementation is demonstrated to the reduce harmonic spectrum and power losses of the proposed system.

The nine-level inverter design is validated using software simulations and hardware prototype testing; the power losses of the proposed inverter design are elaborated and compared with the traditional approach.

This paper aims to propose a bidirectional hidden converter (BHC)-based three-phase DC–AC conversion for energy storage application. BHC is the new concept to vary an energy storage device voltage into wide range. Hidden converter power loss and power rating are reduced by using zero-sequence injection-based carrier-based pulse-width modulation (CBPWM) strategy.

By using this control strategy, a BHC processes only little amount of power during double-stage conversion, mostly during direct or single-stage conversion of the three-phase three-port converter (TPTPC) only processing the maximum power.

TPTPC consists of two sets of positive group switches for inversion process, one set of switches is regular inverter switches called vertical positive group switches, and the second set is anti-series switches, which are horizontally connected for direct or single-stage conversion.

Characteristics, principles and implementations of proposed DC–AC 3Ø conversion system and its PWM strategy are analyzed. Through experimental outputs, the effectiveness and viability of the proposed solutions are validated.