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Closed form solutions of the potential difference between the two depletion layer edges of a single‐diffused Gaussian p‐n junction are obtained by integrating Poisson's equation and equating the positive and negative charges in the depletion layer. Using the closed form solution of the Poisson's equation, the depletion layer width, junction capacitance and junction built‐in potential are calculated. The customary exponential factor m in the expression for the junction capacitance, i.e., Cj α(1 + Va/φ)−m is shown to vary with the applied reverse bias. The value of φ is found to be different from the conventional value of the junction built‐in potential especially at high voltages. A technique for modeling diffused p‐n junctions at various reverse biases is presented. These results will be useful in circuit simulation programs such as SPICE, particularly for applications involving digital integrated circuits.

The purpose of this paper is to compare different junctions' parameters extraction models.

I‐V curves of p⁺‐n and p_well‐n diodes were measured. Five models for parameters extraction on I‐V characteristics of diodes in an educational poly‐Si gate p_well complementary metal oxide semiconductor (CMOS) technology were applied. The junctions' areas were 30 × 30 μm for the source‐body p⁺‐n junction of the PMOS transistor and 220 × 250 μm for the p_well‐body junction. The diodes were sintered in forming gas (10 percent of H₂) in the temperature interval of 450‐525°C for times from 30 min up to 4 h.

It was shown that the best annealing regimes are different for both kinds of junctions.

The paper shows that the best annealing regime for p⁺‐n diodes (the lowest n and I₀ values) is 450°C, 30 min and for the p_well‐n diodes (the lowest I₀ values) is 525°C, 60 min. So, for the different kinds of junctions in one integrated circuit, different annealings could give the best parameters and the optimization depends on the specific characteristics of the developed technology.

The depletion layer of a single‐diffused with complementary error function profile has been calculated. Closed form solutions of the potential difference between the two depletion layer edges are obtained by integrating Poisson's equation and equating the positive and negative charges in the depletion layer. Using the integrability of complementary error functions, the depletion layer thickness, junction built‐in potential and junction exponential factor are computed. The customary exponential factor m in the expression for the junction capacitance, i.e. Cj ∝(1 + Valø)−m is shown to vary with the applied reverse bias. The value of ø is also found to be different from the conventional value of the junction built‐in potential. A technique for modelling the diffused p‐n junctions at various reverse biases is presented using numerical methods. These results will be useful in circuit simulation programs such as SPICE.

In this paper, we consider p–n-junctions, manufactured by diffusion or ion implantation in a heterostructures. We analyzed influence of existing in heterostructure mismatch induced stresses on the current-voltage characteristics of the p–n-junctions. We also introduce an analytical approach for analysis of mass and heat transfer in heterostructures with account changes of their parameters on time, as well as their nonlinearity and mismatch induced stresses. In this paper we introduce an analytical approach for prognosis of the considered processes.

In this paper, we consider p–n-junctions, manufactured by diffusion or ion implantation in a heterostructures. We analyzed influence of existing in heterostructure missmatch induced stresses on the current-voltage characteristics of the p–n-junctions. We also introduce an analytical approach for analysis of mass and heat transfer in heterostructures with account changes of their parameters on time, as well as their nonlinearity and missmatch induced stresses. In this paper we introduce an analytical approach for prognosis of the considered processes.

In this paper, we consider p–n-junctions, manufactured by diffusion or ion implantation in a heterostructures. We analyzed influence of existing in heterostructure missmatch induced stresses on the current-voltage characteristics of the p–n-junctions. We also introduce an analytical approach for analysis of mass and heat transfer in heterostructures with account changes of their parameters on time, as well as their nonlinearity and missmatch induced stresses. In this paper we introduce an analytical approach for prognosis of the considered processes.

This paper is original.

The basis of most semi‐conductor devices is the p‐n junction. Here p‐type material is brought into contact with n‐type material by a suitable process so that between the two types of material we have a zone of transition — the depletion layer. This layer spans the region where purely p‐type properties change to purely n‐type. On one side of the layer there are many holes in the valence band and on the other there are many electrons in the conduction band. How we present this state of affairs to the student may be open to question, but, as electrons are the particles which move, it is considered better to represent the conduction electrons as possessing higher energy, i.e. to let electron energy be considered to be positive upward in any model or diagram produced to explain the p‐n junction and its rectifying properties.

The optimisation of grid structure and relaxation parameter is considered in this paper in connection with two‐dimensional finite difference solution of Poisson's equation for determining the field profile in a reverse biased planar type p?n junction. By dividing the planar junction into regions with rectangular and circular symmetry, regional optimisations have been carried out using small area test sites. Having obtained the optimal grid size and relaxation parameter for each region, the complete solution was obtained easily with very fast convergence. The method involved in this kind of regional optimisation is presented in detail with discussions on its comparative usefulness with other known techniques.

This study investigates the impact of three parameters such as: number of LED chips, pitch and LED power on the junction temperature of LEDs using a best heat sink configuration selected according to a lower temperature. This study provides valuable insights into how to design LED arrays with lower junction temperatures.

To determine the best configuration of a heat sink, a numerical study was conducted in Comsol Multiphysics on 10 different configurations. The configuration with the lowest junction temperature was selected for further analysis. The number of LED chips, pitch and LED power were then varied to determine the optimal configuration for this heat sink. A general equation for the average LED temperature as a function of these three factors was derived using Minitab software.

Among 10 configurations of the rectangular heat sink, we deduce that the best configuration corresponds to the first design having 1 mm of width, 0.5 mm of height and 45 mm of length. The average temperature for this design is 50.5 C. For the power of LED equal to 50 W–200 W, the average temperature of this LED drops when the number of LED chips reduces and the pitch size decreases. Indeed, the best array-LED corresponds to 64 LED chips and a pitch size of 0.5 mm. In addition, a generalization equation for average temperature is determined as a function of the number of LED chips, pitch and power of LED which are key factors for reducing the Junction temperature.

The study is original in its focus on three factors that have not been studied together in previous research. A numerical simulation method is used to investigate the impact of the three factors, which is more accurate and reliable than experimental methods. The study considers a wide range of values for the three factors, which allows for a more comprehensive understanding of their impact. It derives a general equation for the average temperature of the LED, which can be used to design LED arrays with desired junction temperatures.

Scientists and engineers have been solving Poisson’s equation in PN junctions following two approaches: analytical solving or numerical methods. Although several efforts have been accomplished to offer accurate and fast analyses of the electric field distribution as a function of voltage bias and doping profiles, so far none achieved an analytic or semi-analytic solution to describe neither a double diffused PN junction nor a general case for any doping profile. The paper aims to discuss these issues.

In this work, a double Gaussian doping distribution is first considered. However, such a doping profile leads to an implicit problem where Poisson’s equation cannot be solved analytically. A method is introduced and successfully applied, and compared to a finite element analysis. The approach is then generalized, where any doping profile can be considered. 2D and 3D extensions are also presented, when symmetries occur for the doping profile.

These results and the approach here presented offer an efficient and accurate alternative to numerical methods for the modeling and simulation of mathematical equations arising in physics of semiconductor devices.

A general 3D extension in the case where no symmetry exists can be considered for further developments.

The paper strongly simplify and ease the optimization and design of any PN junction.

This paper provides a novel method for electric field distribution analysis.

SINCE the early years of the last decade a great deal of research has been done on the properties of the new class of materials called semiconductors because their electrical properties lie between those of conductors and insulators. Some of the results of these researches are described in this article, in particular those which are of interest to aircraft engineers. A simple explanation of the mechanism of these devices is given and some emphasis is laid on work done by staff and students of the Department of Aircraft Electrical Engineering at The College of Aeronautics.

The aim of this paper is to find the electrical representation of a solid oxide fuel cell (SOFC) that enables the application of typical exploitation characteristics of fuel cells for estimation of fuel cell parameters (for example, exchange current) and easy analysis of phenomena occurred during the fuel cell operation.

Three-layer structure of an SOFC, where a thin semi-conducting layer of electrolyte separates the anode from the cathode, shows a strong similarity to typical semiconductor devices built on the basis of P-N junctions, like diodes or transistors. Current–voltage (I-V) characteristics of a fuel cell can be described by the same mathematical functions as I-V plots of semiconductor devices. On the basis of this similarity and analysis of impedance spectra of a real fuel cell, two electrical representations of the SOFC have been created.

The simplified electrical representation of SOFC consists of a voltage source connected in series with a diode, which symbolizes a voltage drop on a cell cathode, and two resistors. This model is based on the similarity of Butler-Volmer to Shockley equation. The advanced representation comprises a voltage source connected in series with a bipolar transistor in close to saturation mode and two resistors. The base-emitter junction of the transistor represents voltage drop on the cell cathode, and the base-collector junction represents voltage drop on the cell anode. This model is based on the similarity of Butler-Volmer equation to Ebers-Moll equation.

The proposed approach based on the Shockley and Ebers-Moll formulas enables the more accurate estimation of the ion exchange current and other fuel cell parameters than the approach based on the Butler-Volmer and Tafel formulas. The usability of semiconductor models for analysis of SOFC operation was proved. The models were successively applied in a new design of a planar ceramic fuel cell, which features by reduced thermal capacity, short start-up time and limited number of metal components and which has become the basis for the SOFC stack design.