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A real-time production scheduling method for semiconductor back-end manufacturing process becomes increasingly important in industry 4.0. Semiconductor back-end manufacturing process is always accompanied by order splitting and merging; besides, in each stage of the process, there are always multiple machine groups that have different production capabilities and capacities. This paper studies a multi-agent based scheduling architecture for the radio frequency identification (RFID)-enabled semiconductor back-end shopfloor, which integrates not only manufacturing resources but also human factors.

The architecture includes a task management (TM) agent, a staff instruction (SI) agent, a task scheduling (TS) agent, an information management center (IMC), machine group (MG) agent and a production monitoring (PM) agent. Then, based on the architecture, the authors developed a scheduling method consisting of capability & capacity planning and machine configuration modules in the TS agent.

The authors used greedy policy to assign each order to the appropriate machine groups based on the real-time utilization ration of each MG in the capability & capacity (C&C) planning module, and used a partial swarm optimization (PSO) algorithm to schedule each splitting job to the identified machine based on the C&C planning results. At last, we conducted a case study to demonstrate the proposed multi-agent based real-time production scheduling models and methods.

This paper proposes a multi-agent based real-time scheduling framework for semiconductor back-end industry. A C&C planning and a machine configuration algorithm are developed, respectively. The paper provides a feasible solution for semiconductor back-end manufacturing process to realize real-time scheduling.

Au stud bump bonding technology is an effective means to realize heterogeneous integration of commercial chips in the 2.5D electronic packaging. The purpose of this paper is to study the long-term reliability of the Au stud bump treated by four different high temperature storage times (200°C for 0, 100, 200 and 300 h).

The bonding strength and the fracture behavior are investigated by chip shear test. The experiment is further studied by microstructural characterization approaches such as scanning electron microscope, energy dispersive spectrometer and so on.

It is recognized that there were mainly three typical fracture models during the chip shear test among all the Au stud bump samples treated by high temperature storage. For solder bump before aging, the fracture occurred at the interface between the Cu pad and the Au stud bump. As the aging time increased, the fracture mainly occurred inside the Au stud bump at 200°C for 100 and 200 h. When aging time increased to 300 h, it is found that the fracture transferred to the interface between the Au stud bump and the Al Pad.

In addition, the bonding strength also changed with the high temperature storage time increasing. The bonding strength does not change linearly with the high temperature storage time increasing but decreases first and then increases. The investigation shows that the formation of the intermetallic compounds because of the reaction between the Au and Al atoms plays a key role on the bonding strength and fracture behavior variation.

This paper aims to present two Anand’s model parameter sets for the multilayer silver–tin (AgSn) transient liquid phase (TLP) foils.

The AgSn TLP test samples are manufactured using pre-defined optimized TLP bonding process parameters. Consequently, tensile and creep tests are conducted at various loading temperatures to generate stress–strain and creep data to accurately determine the elastic properties and two sets of Anand model creep coefficients. The resultant tensile- and creep-based constitutive models are subsequently used in extensive finite element simulations to precisely survey the mechanical response of the AgSn TLP bonds in power electronics due to different thermal loads.

The response of both models is thoroughly addressed in terms of stress–strain relationships, inelastic strain energy densities and equivalent plastic strains. The simulation results revealed that the testing conditions and parameters can significantly influence the values of the fitted Anand coefficients and consequently affect the resultant FEA-computed mechanical response of the TLP bonds. Therefore, this paper suggests that extreme care has to be taken when planning experiments for the estimation of creep parameters of the AgSn TLP joints.

In literature, there is no constitutive modeling data on the AgSn TLP bonds.

The purpose of this study is to propose a simplifying approach for modelling a reliability test. Modelling the reliability tests of printed circuit board (PCB)/microelectronic component assemblies requires the adoption of several simplifying assumptions. This study introduces and validates simplified assumptions for modeling a four-point bend test on a PCB/wafer-level chip scale packaging assembly.

In this study, simplifying assumptions were used. These involved substituting dynamic imposed displacement loading with an equivalent static loading, replacing the spherical shape of the interconnections with simplified shapes (cylindrical and cubic) and transitioning from a three-dimensional modelling approach to an equivalent two-dimensional model. The validity of these simplifications was confirmed through both quantitative and qualitative comparisons of the numerical results obtained. The maximum principal plastic strain in the solder balls and copper pads served as the criteria for comparison.

The simplified hypotheses were validated through quantitative and qualitative comparisons of the results from various models. Consequently, it was determined that the replacement of dynamic loading with equivalent static loading had no significant impact on the results. Similarly, substituting the spherical shape of interconnections with an equivalent shape and transitioning from a three-dimensional approach to a two-dimensional one did not substantially affect the precision of the obtained results.

This study serves as a valuable resource for researchers seeking to model accelerated reliability tests, particularly in the context of four-point bending tests. The results obtained in this study will assist other researchers in streamlining their numerical models, thereby reducing calculation costs through the utilization of the simplified hypotheses introduced and validated herein.

This study aims to contribute to the numerical modelling of drop impact on a flip-chip component assembled on printed circuit boards using solder micro-bumps. This contribution is based on the introduction of non-linear fracture mechanics in the numerical approach.

The integration of non-linear fracture mechanics into the numerical approach requires the proposal and validation of several simplifying assumptions. Initially, a dynamic 3D model was simplified to a dynamic 2D model. Subsequently, the dynamic 2D model is replaced with an equivalent static 2D model. The equivalent static 2D model was used to perform calculations considering the non-linear fracture mechanics. A crack was modelled in the critical bump. The J-integral was used as a comparative parameter to study the effects of crack length, crack position and chip thickness on the fracture toughness of the solder bump.

The different simplifying assumptions were validated by comparing the results obtained by the various models. Numerical results showed a high risk of failure at the critical solder bump in a zone close to the intermetallic layer. The obtained results were in agreement with the post-test observations using the “Dye and Pry” methods.

The originality of this study lies in the introduction of non-linear fracture mechanics to model the mechanical response of solder bumps during drop impact. This study led to some interesting conclusions, highlighting the advantage of introducing non-linear fracture mechanics into the numerical simulations of microelectronic components during a drop impact.

The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.

To obtain an efficient, high-gain and high-power performance with in a compact and low-cost size, the prototype is based on Gallium nitride (GaN) on SiC 0.25-µm transistors, whereas the passive matching networks are realized on an AlN substrate as thin film circuit.

Measured results of the q-MMIC PA across the 0.2 to 2.2 GHz band show at least 32 ± 3 dB small-signal gains, an output power of 7 to 12 W and an average power add efficiency greater than 54%. The q-MMIC occupies an area of 12.8 × 14.5 mm².

To the best of the authors’ knowledge, this work reports the first full integrated PA which covers the frequency range of 0.2 to 2.2 GHz and achieves the combination of highest gain, about 10 W output power, together with the smallest component size among all published GaN PAs to date.

Identification of the direction of the sound source is very important for human–machine interfacing in the applications such as target detection on military applications and wildlife conservation. Considering its vast applications, this study aims to design, simulate, fabricate and test a bidirectional acoustic sensor having two cantilever structures coated with piezoresistive material for sensing has been designed, simulated, fabricated and tested.

The structure is a piezoresistive acoustic pressure sensor, which consists of two Kapton diaphragms with four piezoresistors arranged in Wheatstone bridge arrangement. The applied acoustic pressure causes diaphragm deflection and stress in diaphragm hinge, which is sensed by the piezoresistors positioned on the diaphragm. The piezoresistive material such as carbon or graphene is deposited at maximum stress area. Furthermore, the Wheatstone bridge arrangement has been formed to sense the change in resistance resulting into imbalanced bridge and two cantilever structures add directional properties to the acoustic sensor. The structure is designed, fabricated and tested and the dimensions of the structure are chosen to enable ease of fabrication without clean room facilities. This structure is tested with static and dynamic calibration for variation in resistance leading to bridge output voltage variation and directional properties.

This paper provides the experimental results that indicate sensor output variation in terms of a Wheatstone bridge output voltage from 0.45 V to 1.618 V for a variation in pressure from 0.59 mbar to 100 mbar. The device is also tested for directionality using vibration source and was found to respond as per the design.

The fabricated devices could not be tested for practical acoustic sources due to lack of facilities. They have been tested for a vibration source in place of acoustic source.

The piezoresistive bidirectional sensor can be used for detection of direction of the sound source.

In defense applications, it is important to detect the direction of the acoustic signal. This sensor is suited for such applications.

The present paper discusses a novel yet simple design of a cantilever beam-based bidirectional acoustic pressure sensor. This sensor fabrication does not require sophisticated cleanroom for fabrication and characterization facility for testing. The fabricated device has good repeatability and is able to detect the direction of the acoustic source in external environment.

This paper aim to solve the problem of low assembly success rate for 3c assembly lines designed based on classical control algorithms due to inevitable random disturbances and other factors,by incorporating intelligent algorithms into the assembly line, the assembly process can be extended to uncertain assembly scenarios.

This work proposes a reinforcement learning framework based on digital twins. First, the authors used Unity3D to build a simulation environment that matches the real scene and achieved data synchronization between the real environment and the simulation environment through the robot operating system. Then, the authors trained the reinforcement learning model in the simulation environment. Finally, by creating a digital twin environment, the authors transferred the skill learned from the simulation to the real environment and achieved stable algorithm deployment in real-world scenarios.

In this work, the authors have completed the transfer of skill-learning algorithms from virtual to real environments by establishing a digital twin environment. On the one hand, the experiment proves the progressiveness of the algorithm and the feasibility of the application of digital twins in reinforcement learning transfer. On the other hand, the experimental results also provide reference for the application of digital twins in 3C assembly scenarios.

In this work, the authors designed a new encoder structure in the simulation environment to encode image information, which improved the model’s perception of the environment. At the same time, the authors used the fixed strategy combined with the reinforcement learning strategy to learn skills, which improved the rate of convergence and stability of skills learning. Finally, the authors transferred the learned skills to the physical platform through digital twin technology and realized the safe operation of the flexible printed circuit assembly task.

By investigating the thermal-mechanical interaction between the through silicon via (TSV) and the Cu pad, this study aimed to determine the effect of electroplating defects on the upper surface protrusion and internal stress distribution of the TSV at various temperatures and to provide guidelines for the positioning of TSVs and the optimization of the electroplating process.

A simplified model that consisted of a TSV (100 µm in diameter and 300 µm in height), a covering Cu pad (2 µm thick) and an internal drop-like electroplating defect (which had various dimensions and locations) was developed. The surface overall deformation and stress distribution of these models under various thermal conditions were analyzed and compared.

The Cu pad could barely suppress the upper surface protrusion of the TSV if the temperature was below 250 ?. Interfacial delamination started at the collar of the TSV at about 250 ? and became increasingly pronounced at higher temperatures. The electroplating defect constantly experienced the highest level of strain and stress during the temperature increase, despite its geometry or location. But as its radius expanded or its distance to the upper surface increased, the overall deformation of the upper surface and the stress concentration at the collar of the TSV showed a downward trend.

Previous studies have not examined the influence of the electroplating void on the thermal behavior of the TSV. However, with the proposed methodology, the strain and stress distribution of the TSV under different conditions in terms of temperature, dimension and location of the electroplating void were thoroughly investigated, which might be beneficial to the positioning of TSVs and the optimization of the electroplating process.

The purpose of this paper is to solve the issue of via filling and pattern plating simultaneously by concentration optimization of accelerator and leveler in the electroplating bath.

This paper designs a series of experiments to verify the performance of pattern plating with the via filling plating formula. Then the compositions of electroplating solution are optimized to achieve via filling and pattern plating simultaneously. Finally, the mechanism of co-plating for via and line is discussed in brief.

To achieve excellent performance for via filling and pattern plating simultaneously, proportion of additives are comprehensively considered in optimization of electroplating process. Effects of additives on the via filling and pattern plating should be taken into consideration, especially in achieving flat lines.

This paper discusses the different effects of accelerator and leveler on the via filling and the pattern plating, respectively. The process of co-plating for the via and the line is presented. The superfilling of via and the flat line are simultaneously obtained with the optimized via filling formula.