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The mechanisms for void formation are investigated for applications involving solder paste in surface mount technology. Generally, voids are caused by the outgassing of entrapped flux in the sandwiched solder during reflow. The voiding is dictated mainly by the solderability of metallisation, and increases with decreasing solderability of metallisation, decreasing flux activity, increasing metal load of powder, and increasing coverage area under the lead of the joint. Decrease in the solder powder particle size has only a slightly negative effect on voiding. The data indicate that voiding is also a function of the timing between the coalescing of solder powder and the elimination of immobile metallisation oxide. The sooner the paste coalescence occurs, the worse the voiding will be. Increase in voiding is usually accompanied by an increasing fraction of large voids, suggesting that factors causing voiding will have an even greater impact on the joint reliability than shown by the total‐ void‐volume analysis results. Preliminary data suggest that certain predry treatment and flux solvent with higher boiling point appear to cause increased voiding.

Voiding in BGA assembly using SN63 solder bumps is primarily introduced at board‐level assembly stage. On the pretinned PCBs, voiding of BGA joints increases with increasing solvent volatility, increasing metal content and increasing reflow temperature, and with decreasing powder size. This can be explained by a viscosity dictated flux‐exclusion‐rate model. In this model, a higher viscosity in the fluxing medium at reflow temperature could hinder the exclusion of flux from the interior of the molten solder, hence increase the chance of outgassing due to the increasing amount of entrapped flux, and consequently result in higher voiding in BGA assembly. Flux activity and reflow atmosphere appear to have a negligible effect on voiding when the solderability of the immobile metallisation is not a concern. An increase in void content is accompanied by an increase in the fraction of large voids. This suggests that, similar to voiding phenomena in the SMT process, factors causing voiding in BGA will have an even greater impact on joint reliability than shown by the total‐void‐volume analysis results.

The purpose of this paper is to employ data mining as a new diagnosing scheme for investigating void formation to the thermal pad in quad flat non‐lead (QFN) assembly. Occurrences of voiding in various scenarios of component design, materials selection and manufacturing process are analyzed.

This research investigates the process yield of a PCB assembly for a handheld device in the electronics manufacturing industry using the chi‐square automatic interaction detection (CHAID) algorithm and chi‐square test. Practical data generated by an X‐ray apparatus from the shop floor are collected. The critical attributes to the void formation (in the solder joint) of the QFN component are identified.

Stocking the PCB material beyond ten days may increase the level of voiding by 1%. Using PCB provided by vendor U helps decrease the level of voiding by 1.6%. Stocking the component material above 43 days may increase the level of voiding by 1.9%. In addition, reflow soldering profile with time above liquid (TAL) less than or equal to 62 sec and with peak temperature higher than or equal to 241°C generate less voids. Finally, the via‐in‐pad design causes a concave geometry on the surface of thermal pad which contributes to the voiding formation. The amount of voiding can be further diminished by plugging the via with plated copper.

This research implements CHAID that extracts useful knowledge from a huge amount of manufacturing data in order to realize the complex interaction effects through automated analysis. The extent of voiding in the samples using the optimal process suggested through CHAID algorithm can be reduced from 16% to 10.2%.

The purpose of this paper is to propose a solution procedure to minimize/eliminate voiding and spattering defects in the assembly of 0201 chip components with micro via‐in pads and 95 wt.%Sn‐5 wt.%Sb solder alloy.

In total, four different micro via‐in pad designs were compared (via‐hole opening size): ultra small via‐in pads (d: 10 μm), small via‐in pads (d: 20 μm), and large via‐in pads (d: 60 μm), as well as designs with no via‐in pads and capped via‐in pads. Two process variables were also evaluated for the goal of achieving a high‐yield assembly solution in micro via‐in pad and lead‐free solder systems. Potential factors, such as the preheat conditions of the reflow profile and stencil aperture size, which might affect voiding and spattering in solder joints with micro via‐in pad, were investigated. Solder voiding frequency and size were also determined from X‐ray inspection and sample cross‐section analysis.

The results indicated that larger via‐holes were seen to create bigger voiding than smaller via‐holes. For smaller via‐holes, spattering is a greater problem than voiding in solder joints. Ultra small via‐in pads generated higher spattering compared to no via‐in pads and capped via‐in pads. Capped via‐in pads exhibited the best results in preventing voiding and flux spattering, and provided a wide process window for the selection of process parameters. It is also indicated that spattering was found to rapidly reduced with both increasing stencil opening size and use of reflow profile with long‐preheat conditions.

The findings provide certain process guidelines for surface‐mount assembly with via‐in pad substrate design. The strategy is to prevent voiding and spattering by adopting capped via‐in pads, if possible, when applying micro via with the 95 wt.%Sn‐5 wt.%Sb solder alloy system.

Tombstoning and voiding have been plaguing the surface mount assembly industry for decades. The recent global move toward lead‐free soldering and the extensive adoption of microvia technology further aggravate the problems. The present study investigates the impact of SnAgCu (SAC) alloy composition on these important issues.

In this study, tombstoning and voiding at microvias are studied for a series of SAC lead‐free solders, with an attempt to identify a possible “composition window” for controlling these problems. Properties which may be related to these problems, such as alloy surface tension, alloy melting pattern, and solder wetting behaviour, were investigated in order to assess the critical characteristics required to control these problems.

The results indicate that the tombstoning of SAC alloys is greatly influenced by the solder composition. Both the wetting force and the wetting time at a temperature well above the melting point have no correlation with the tombstoning frequencies. Because the tombstoning is caused by imbalanced wetting forces, the results suggest that the tombstoning may be controlled by the wetting at the onset of the paste melting stage. A maximum tombstoning incidence was observed for the 95.5Sn3.5Ag1Cu alloy. The tombstoning rate decreased with increasing deviation in Ag content from this composition. A differential scanning calorimetry (DSC) study indicated that this was mainly due to the increasing presence of the pasty phase in the solders, which result in a slower wetting speed at the onset of solder paste melting stage. Surface tension plays a minor role, with lower surface tension correlating with a higher tombstoning rate. The voiding rate at the microvias was studied by employing simulated microvias. The voiding level was lowest for the 95.5Sn3.8Ag0.7Cu and 95.5Sn3.5Ag1Cu alloys, and increases with a further decrease in the Ag content. The results indicate that voiding at microvias is governed by the via filling and the exclusion of fluxes. The voiding rate decreased with decreasing surface tension and increasing wetting force, which in turn is dictated by the solder wetting or spreading. Both low surface tension and high solder wetting prevents the flux from being entrapped within a microvia. A fast wetting speed may also facilitate reducing voiding. However, this factor is considered not as important as the final solder coverage area.

In general, compositions which deviate from the ternary eutectic SAC in Ag content, particularly with a Ag content lower than 3.5Ag, exhibit a greater solid fraction at the onset of melting, resulting in a lower tombstoning rate, presumably due to a slower wetting speed. The SAC compositions with an Ag content lower than 3.5 per cent, such as 2.5Ag, resulted in a lower tombstoning rate with minimal risk of forming Ag₃Sn intermetallic platelets. On the other hand, ternary eutectic SAC exhibits a lower surface tension resulting in an easier solder spread or solder wetting, and consequently exhibit a higher tombstoning frequency and a lower incidence of voiding.

Provides a solution to the tombstoning problem in lead‐free soldering.

The present study provided a solution to the tombstoning problem encountered in lead free soldering by controlling the SAC solder alloy compositions.

The rapid progress of ball grid array (BGA) component technology has served to alleviate many problems associated with the placement and soldering of high lead count, fine pitch surface mount technology (SMT) packages. An unfortunate result of this process, however, is the occurrence of voids in the interconnecting eutectic solder balls of these packages. Large voids can affect the mechanical and thermal properties of the interconnect, which can reduce a component’s mean time‐to‐failure and may also affect the transmission of high frequency electrical signals through the solder ball. For this reason, several experiments were conducted to investigate the manner and mechanisms in which voids are introduced into eutectic BGA solder ball joints. The following process parameters were found to be the primary parameters responsible for the voiding phenomenon: condition of the component’s alloy and substrate, oxygen concentration in the reflow atmosphere, solder paste properties and the reflow profile. Through modification and optimization of process parameters in the manufacturing environment, BGA solder joint voiding was greatly reduced.

The purpose of this paper is to evaluate the influence of microvia design on solder joint reliability and to present a printed circuit board (PCB) microvia design approach capable of reducing or eliminating voiding in solder joints.

Five different types of via‐in‐pad designs were incorporated into a test vehicle and their performance evaluated using a variety of standard reliability tests.

Solid vias, composed of 99.5 percent pure copper can be used to eliminate voiding in solder joints. Such vias are also much more robust than those employing metallic paste or other filled materials. Solid vias with flat surfaces have been shown to be able to meet the requirements of common reliability test standards and to offer a process compatible with traditional PCB manufacturing.

The occurrence of voiding in solder joints has been shown to be significantly influenced by microvia design. Although a design is reported for reducing/eliminating voiding, other factors that can cause voiding should be investigated. Also, further extended accelerated reliability testing could be undertaken to determine comparative long‐term reliability.

Serious voiding in solder joints is a major threat to the quality and reliability of electronics assemblies, mainly due to its role as a stress concentrator and particularly with the move to lead‐free assembly. Methods for reducing and eliminating the occurrence of voiding are needed by electronics assemblers and this work proposes one such method that can be implemented at the circuit board design stage.

This paper aims to investigate voiding phenomena in solder joints under thermal pads of light-emitting diodes (LEDs) assembled in mass production environment by reflow soldering by using seven low-voiding lead-free solder pastes.

The solder pastes investigated are of SAC305 type, Innolot type or they are especially formulated by the manufacturers on the base of (SnAgCu) alloys with addition of some alloying elements such as Bi, In, Sb and Ti to provide low-void contents. The SnPb solder paste – OM5100 – was used as a benchmark. The solder paste coverage of LED solder pads was chosen as a measure of void contents in solder joints because of common usage of this parameter in industry practice.

It was found that the highest coverage and, related to it, the least void contents are in solder joints formed with the pastes LMPA-Q and REL61, which are characterized by the coverage of mean value 93.13% [standard deviation (SD) = 2.72%] and 92.93% (SD = 2.77%), respectively. The void diameters reach the mean value equal to 0.061 mm (SD = 0.044 mm) for LMPA-Q and 0.074 mm (SD = 0.052 mm) for REL61. The results are presented in the form of histograms, plot boxes and X-ray images. Some selected solder joints were observed with 3D computer tomography.

The statistical analyses are carried out on the basis of 2D X-ray images with using Origin software. They enable to compare features of various solder pastes recommended by manufacturers as low voiding. The results might be useful for solder paste manufacturers or electronic manufacturing services.

Two new electrolytically plated lead‐free surface finishes are evaluated for their wettability, bond strength, and voiding performance, and are compared with electrolytic nickel gold and an OSP. The results indicate that Ni–Sn achieve the highest wettability, one of the highest lap shear strengths, and the lowest levels of voiding. It also performs better under a long reflow profile. Under most instances, the soldering performance is comparable with, or better than, the reference OSP and Ni–Au surface finishes. Ni–PdCo–Au was found to give a poor wettability, fairly low lap shear strength, and have high levels of voiding. However, it is fairly stable, and its soldering performance is not sensitive to the reflow profile length or atmosphere, aging treatment, or flux chemistry. OSP was found to be the poorest in terms of wettability, but one of the best for lap shear strength. It also performs best under long profile, is not sensitive to reflow atmosphere, is slightly sensitive to alloy type, but is very sensitive to aging and flux chemistry.

To investigate the degradation of lead free solder heat‐sink attachment by thermal shock. Samples with high voiding percentages were selected for the investigation in order to get information on the significance of voids on the reliability of Sn‐Ag‐Cu heat‐sink attachment.

Through the use of X‐ray, C‐mode scanning acoustic microscopy, dye penetration, cross section and scanning electron microscopy/energy‐dispersive X‐ray tests, the degradation of Sn‐Ag‐Cu heat‐sink attachment during thermal shock cycling was evaluated.

The results showed that the Sn‐Ag‐Cu heat‐sink attachment where the area of voiding was 33‐48 per cent survived 3,000 thermal shock cycles, although degraded. The main degradation mechanism for the solder attachment was not solder fatigue but interface delamination due to Kirkendall voids at the Cu/Cu₃Sn interface. It was found that the large voids in the Sn‐Ag‐Cu heat‐sink attachment were not significantly affecting the solder joint lifetime. Big differences of intermetallic compound growth behaviour and Kirkendall voids at device/solder and solder/Cu pad interfaces are found and the reasons for this are discussed.

This work has clarified the general perception that large voids affect the thermo‐mechanical lifetime of solder joint substantially and also provides further understanding of the Sn‐Ag‐Cu heat‐sink attachment degradation mechanism.