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This paper aims to investigate the moisture diffusion behavior in a system-in-package module systematically by moisture-thermalmechanical-coupled finite element modeling with different structure parameters under increasingly harsh environment.

A finite element model for a system-in-package module was built with moisture-thermal-mechanical-coupled effects to study the subsequences of hygrothermal conditions.

It was found in this paper that the moisture diffusion path was mainly dominated by hygrothermal conditions, though structure parameters can affect the moisture distribution. At lower temperatures (30°C~85°C), the direction of moisture diffusion was from the periphery to the center of the module, which was commonly found in simulations and literatures. However, at relatively higher temperatures (125°C~220°C), the diffusion was from printed circuit board (PCB) to EMC due to the concentration gradient from PCB to EMC across the EMC/PCB interface. It was also found that there exists a critical thickness for EMC and PCB during the moisture diffusion. When the thickness of EMC or PCB increased to a certain value, the diffusion of moisture reached a stable state, and the concentration on the die surface in the packaging module hardly changed. A quantified correlation between the moisture diffusion coefficient and the critical thickness was then proposed for structure parameter optimization in the design of system-in-package module.

The different moisture diffusion behaviors at low and high temperatures have seldom been reported before. This work can facilitate the understanding of moisture diffusion within a package and offer some methods about minimizing its effect by design optimization.

To present key challenges associated with the evolution of system‐in‐package technologies and present technical work in reliability modeling and embedded test that contributes to these challenges.

Key challenges have been identified from the electronics and integrated MEMS industrial sectors. Solutions to optimising the reliability of a typical assembly process and reducing the cost of production test have been studied through simulation and modelling studies based on technology data released by NXP and in collaboration with EDA tool vendors Coventor and Flomerics.

Characterised models that deliver special and material dependent reliability data that can be used to optimize robustness of SiP assemblies together with results that indicate relative contributions of various structural variables. An initial analytical model for solder ball reliability and a solution for embedding a low cost test for a capacitive RF‐MEMS switch identified as an SiP component presenting a key test challenge.

Results will contribute to the further development of NXP wafer level system‐in‐package technology. Limitations are that feedback on the implementation of recommendations and the physical characterisation of the embedded test solution.

Both the methodology and associated studies on the structural reliability of an industrial SiP technology are unique. The analytical model for solder ball life is new as is the embedded test solution for the RF‐MEMS switch.

The purpose of this paper is to demonstrate a novel 3D system-in-package (SiP) approach. This new packaging approach is based on stacked silicon submount technology. As demonstrators, a smart lighting module and a sensor systems were successfully developed by using the fabrication and assembly process described in this paper.

The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. This platform consists of silicon submount design and fabrication, module packaging, system assembling and testing and analyzing.

In this paper, a smart light emitting diode system and sensor system will be described based on stacked silicon submount and 3D SiP technology. The integrated smart lighting module meets the optical requirements of general lighting applications. The developed SiP design is also implemented into the miniaturization of particular matter sensors and gas sensor detection system.

SiP has great potential of integrating multiple components into a single compact package, which has potential implementation in intelligent applications.

This study aims to provide a flexible and cost-effective solution of 3D heterogeneous integration for applications such as micro-electro-mechanical system (MEMS) applications and smart sensor systems.

A novel 3D system-in-package (SiP) based on stacked silicon submount technology was successfully developed and well-demonstrated by the fabrication and assembly process of a selected smart lighting module.

The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The bonding and interconnecting process is quite simple and does not require complicated equipment. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. The submount wafer can be assembled and tested at the wafer level, thus reducing the cost and improving the yield.

The embedding design presented in this paper is applicable for modules with limited number of passives. When it comes to cases with more passive devices, new process needs to be developed to achieve fast, inexpensive and reliable assembly.

The presented 3D SiP design is novel for applications such as smart lighting, Internet of Things, MEMS systems, etc.

This paper aims to study a high-temperature (up to 200 °C) data acquisition and processing circuit for logging.

With the decrease in thermal resistance by system-in package technology and exquisite power consumption distribution design, the circuit worked well at high temperatures environment from both theoretical analysis and real experiments evaluation.

In thermal simulation, considering on board chips’ power consumption as additional heat source, the highest temperature point reached by all the chips in the circuit is only 211 °C at work temperature of 200 °C. In addition, the proposed circuit was validated by long time high-temperature experiments. The circuit showed good dynamic performance during a 4-h test in a 200-°C oven, and maintained a signal-to-noise ratio of 92.54 dB, a signal-to-noise and distortion ratio of 91.81 dB, a total harmonic distortion of −99.89 dB and a spurious free dynamic range of 100.28 dB.

The proposed circuit and methodology showed great potential for application in deep-well logging systems and other high-temperature situations.

Traditional nondestructive failure localization techniques are increasingly difficult to meet the requirements of high density and integration of system in package (SIP) devices in terms of resolution and accuracy. Time domain reflection (TDR) is recognized as a novel positioning analysis technology gradually being used in the electronics industry because of the good compatibility, high accuracy and high efficiency. However, there are limited reports focus on the application of TDR technology to SiP devices.

In this study, the authors used the TDR technique to locate the failure of SiP devices, and the results showed that the TDR technique can accurately locate the cracking of internal solder joints of SiP devices.

The measured transmission rate of electromagnetic wave signal was 9.56 × 107 m/s in the experimental SiP devices. In addition, the TDR technique successfully located the failure point, which was mainly caused by the cracking of the solder joint at the edge of the SiP device after 1,500 thermal cycles.

TDR technology is creatively applied to SiP device failure location, and quantitative analysis is realized.

This study aims to focus on the passive components of System in Package SiP modules and discusses the geometric pad designs for 01005-sized passive components, the front end design of the hole size and shape of the stencil and the parameters of the stencil sidewall coating, to determine the optimum parameter combination.

This study plans and conducts experiments, where a L8(27) inner orthogonal array is built to consider the control factors, including a L4(23) outer orthogonal array to consider the noise factor, and the experimental data are analyzed by using the technique for order preference by similarity to ideal solution multi-quality analysis method.

The results show that the optimum design parameter level combination is that the solder mask opening pad has no solder mask in the lower part of the component, the pad width is 1.1 times that of the component width, the pad length is 1.75 times that of the electrode tip length, the pad spacing is 5 mil, the stencil open area is 90% of the pad area, the stencil opening corner has a 3 mil chamfer angle, and the stencil sidewall is free of nano-coating.

The parameter design and multi-quality analysis method, as proposed in this study, can effectively develop the layout of passive components on a high-density SiP module substrate, to stabilize the process and increase the production yield.

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.