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The paper aims to consider the problem of the influence of mounting power metal-oxide semiconductor (MOS) transistors operating in the Totem–Pole circuit on energy losses in this circuit.

Using the computer simulation in SPICE software, the influence of such factors as on-state resistance of the channel of the MOS transistor, the self-heating phenomena in this transistor and resistance of wires connecting transistors with the other part of the circuit on characteristics of the considered circuit operating with resistor, inductor and capacitor (RLC) load is analyzed. The selected results of calculations are compared with the results of measurements.

On the basis of the obtained results of calculations, some recommendations concerning the manner of mounting the considered transistors, assuring a high value of watt-hour efficiency of the process of energy transfer to the load are formulated.

The investigations were performed in the wide range of the frequency of the signal stimulating the considered circuit, but the results of calculations were presented for 2 selected values of this frequency only.

The considered analysis was performed for the circuit dedicated to power supplied of an elecrolyser.

Presented results of calculations prove that in some situations, the value of watt-hour efficiency of the considered circuit is determined by the length and the cross-section area of the applied wires bringing the signal to the connectors of the transistors and to load. On the other hand, self-heating phenomena in the power MOS transistors can lead to doubling power losses in these devices.

The purpose of this paper is to present the high-frequency performance of 0.13-μm n-type metal-oxide-semiconductor (NMOS) transistors with various multi-finger configurations for implementation in millimeter-wave (mm-wave) frequency.

A folded-like double-gate transistor layout is designed to enable the transistor to work in the mm-wave region. Different sizes of transistors with variation in finger width (W_F ) and number of fingers (N_F ) were fabricated to determine the optimum size of the transistor. The extrinsic parasitic elements of selected transistors were extracted and investigated. The radio frequency (RF) performance of these samples were then analyzed and compared.

The proposed layout performed well with the highest maximum oscillation frequency (f_max ) achieved at 122 GHz. Based on the comparison done, the optimum W_F obtained for the layout is at 2.0 μm. It is found that the extrinsic parasitic capacitance is more dominant than the parasitic resistance in affecting the f_max . In s-parameter analysis, it is observed that the transistor with the least N_F has smaller variance in small-signal gain throughout the measurement frequency. The maximum stable gain for the samples is also found to be roughly similar and independent of N_F .

A new layout structure for an NMOS transistor that works in mm-wave frequency is proposed. Experimental analyses presented here cover for both N_F and W_F , unlike others which focus on either N_F or W_F only.

This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell.

The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate.

Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively.

The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

In order to simulate resistive gate transistors, a one‐dimensional simulator, which permits the use of multiple gate contacts on the transistor structure, has been developed. In the case of the multiple gate contact resistive gate transistor, there is a voltage gradient in the gate. The gate voltage thus varies at each point in the channel of the transistor. A gate structure was designed with a geometric profile that gave either a decreasing or an increasing electric field in the gate, depending on the differential voltage applied to the gate contacts. In the saturation region, this parabolically shaped gate structure resulted in a linear relationship between the drain current and the differential gate voltage or gate current. A significant result obtained was the reversal of the drift current direction at certain bias levels. It was also found that the diffusion current may dominate in the strong inversion region of the channel of an NMOS transistor with a resistive gate.

This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.

The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.

The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

The Monte‐Carlo particle model is a technique of simulating small semiconductor devices. It consists briefly of following the detailed transport histories of individual carriers, their time of free flight and consequent scattering chosen by a random number technique. A description of the method is given. The method has proved itself successful in semiconductor analysis, and as an example of its application we are using it to study the influence the epitaxial doping has on the performance of field‐effect transistors. We are comparing a transistor with an epitaxially grown active layer, with one with an ion implanted active layer and with an ideal device with an abrupt transition between the epilayer and the substrate. The cut‐off bias for ideal transistor is found to be more sharply defined than for the other two types of transistors. The spatial distribution of the carriers follows roughly the doping profile near the source. Underneath the gate the peak of the carrier density is pushed further down and into the substrate as the gate bias increases. This peak also weakens as the gate bias rises, and vanishes at, and beyond cut‐off. In the high field region after the gate the upper valleys population increases with increased drain bias and decreases with increased gate bias. The power gain and the y‐parameters are examined for all devices, both near pinch‐off and for no external gate bias. In both cases the ion implanted transistor shows the greatest gain. This transistor also exhibits the lowest minimum noise figure.

This paper aims to find a closed-form expression for the frequency and amplitude of single-ended ring oscillators when transistors experience all regions.

In this paper, the analytical relationships presented for ring oscillator amplitude and frequency are approximately derived due to the nonlinear nature of this oscillator, taking into account the differential equation that governs the ring oscillator and its output waveform.

In the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. The relationship is presented for the frequency, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case.

The validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18 µm technology.

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.