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Article
Publication date: 1 August 2016

Pawel Górecki and Krzysztof Górecki

The paper aims to consider the problem of the influence of mounting power metal-oxide semiconductor (MOS) transistors operating in the Totem–Pole circuit on energy losses in this…

Abstract

Purpose

The paper aims to consider the problem of the influence of mounting power metal-oxide semiconductor (MOS) transistors operating in the Totem–Pole circuit on energy losses in this circuit.

Design/methodology/approach

Using the computer simulation in SPICE software, the influence of such factors as on-state resistance of the channel of the MOS transistor, the self-heating phenomena in this transistor and resistance of wires connecting transistors with the other part of the circuit on characteristics of the considered circuit operating with resistor, inductor and capacitor (RLC) load is analyzed. The selected results of calculations are compared with the results of measurements.

Findings

On the basis of the obtained results of calculations, some recommendations concerning the manner of mounting the considered transistors, assuring a high value of watt-hour efficiency of the process of energy transfer to the load are formulated.

Research limitations/implications

The investigations were performed in the wide range of the frequency of the signal stimulating the considered circuit, but the results of calculations were presented for 2 selected values of this frequency only.

Practical implications

The considered analysis was performed for the circuit dedicated to power supplied of an elecrolyser.

Originality/value

Presented results of calculations prove that in some situations, the value of watt-hour efficiency of the considered circuit is determined by the length and the cross-section area of the applied wires bringing the signal to the connectors of the transistors and to load. On the other hand, self-heating phenomena in the power MOS transistors can lead to doubling power losses in these devices.

Details

Microelectronics International, vol. 33 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 7 August 2017

Krzysztof Górecki and Paweł Górecki

This paper aims to propose the electrothermal dynamic model of the insulated gate bipolar transistors (IGBT) for SPICE.

Abstract

Purpose

This paper aims to propose the electrothermal dynamic model of the insulated gate bipolar transistors (IGBT) for SPICE.

Design/methodology/approach

The electrothermal model of this device (IGBT), which takes into account both electrical and thermal phenomena, is described. Particularly, the sub-threshold operation of this device is considered and electrical, and thermal inertia of this device is taken into account. Attention was focused on the influence of electrical and thermal inertia on waveforms of terminal voltages of the considered transistor operating in the switching circuit and on waveforms of the internal temperature of this device.

Findings

The correctness of the presented model is verified experimentally and a good agreement of the calculated and measured electrical and thermal characteristics of the considered device is obtained.

Research limitations/implications

The presented model can be used for different types of IGBT, but it is dedicated for SPICE software only.

Originality/value

The form of the worked out model is presented and the results of experimental verification of this model are shown.

Details

Microelectronics International, vol. 34 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 1 January 2013

François Maeght, Désiré D. Rasolomampionona, Pierre‐Yves Cresson and Patrick Favier

The aim of this paper is to assemble an experimental solar‐based charging station for electric vehicles. This global system integrates a photovoltaic station, electric vehicles…

Abstract

Purpose

The aim of this paper is to assemble an experimental solar‐based charging station for electric vehicles. This global system integrates a photovoltaic station, electric vehicles and a supervision base. The communication has been set up through a wireless network. This paper presents this project realized by different groups of foreign students working through an International Collaboration in Engineering Education.

Design/methodology/approach

The approach is based on connecting technical research with engineering education. For a few years, the need of further research on renewable energies has leaded to the initiation of several student projects at the university. A group of co‐operating foreign students working together within the framework of a technically innovative subject has been created through the international relations activity of the University of Artois, at IUT of Bethune (Institut Universitaire de Technologie), situated in the northern region of France.

Findings

A prototype of the recharging station has been built. The measures of the energetic performances showed a good efficiency. The data exchange through the wireless network is operating properly and a computer‐based supervising unit is responsible for the coordination of the station/vehicle control. The established international collaboration has demonstrated the possibility of carrying out common students' projects.

Originality/value

The originality of this paper is coming from the major subjects of sustainability such as renewable energies and transportation. A solar‐based station has been built and supplies electric vehicles. The wireless communication has been applied in order to perform control on long distances. This international collaboration is an innovative way for enhancing the collaboration performance in engineering education.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 32 no. 1
Type: Research Article
ISSN: 0332-1649

Keywords

Article
Publication date: 1 August 2016

Agata Skwarek

Abstract

Details

Microelectronics International, vol. 33 no. 3
Type: Research Article
ISSN: 1356-5362

Article
Publication date: 3 April 2018

Hyung-won Kim, Hyeim Jeong, Junho Yu, Chan-Soo Lee and Nam-Soo Kim

This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.

Abstract

Purpose

This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.

Design/methodology/approach

The integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.

Findings

Experiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.

Originality/value

The proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

Details

Microelectronics International, vol. 35 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 3 February 2020

Afreen Khursheed and Kavita Khare

This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device…

Abstract

Purpose

This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm.

Design/methodology/approach

Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control.

Findings

An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes.

Originality/value

Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.

Details

Circuit World, vol. 46 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 23 March 2023

Amrita Sajja and S. Rooban

The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.

Abstract

Purpose

The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.

Design/methodology/approach

This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.

Findings

The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.

Research limitations/implications

All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.

Practical implications

The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.

Originality/value

The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

Details

Microelectronics International, vol. 40 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 27 July 2012

Yasin Özcelep and Ayten Kuntman

The purpose of this paper is to propose a time‐dependent mobility degradation model which is independent from the process or operating conditions.

Abstract

Purpose

The purpose of this paper is to propose a time‐dependent mobility degradation model which is independent from the process or operating conditions.

Design/methodology/approach

In total, four transistors under test are electrically stressed using constant positive electrical stress voltage technique with the gate bias of VG=40 V DC, where the source and drain were grounded. The authors increased the stress voltage step by step to avoid electrostatic discharge and recorded the ID‐VDS and ID‐VGS measurements in time intervals during the stress.

Findings

The experimental results show that the output current and the threshold voltage of the transistor are increased after the stress. Mobility and channel length are decreased. The changes in the transistor parameters were associated to interface state Si/SiO2 effects. The authors used the physical changes in transistor and proposed a new‐time dependent mobility degradation model. The mobility change was calculated using the proposed model and compared with the experimental results. It was seen that the calculated and experimental results are in good agreement.

Originality/value

This is an original research paper and enables the mobility degradation to be predicted independently from effects of process or operational changes such as oxide thickness, substrate doping, and applied voltages on transistor.

Abstract

Details

Strategic Business Models: Idealism and Realism in Strategy
Type: Book
ISBN: 978-1-78756-709-2

Article
Publication date: 1 April 1993

P Schieke and M du Plessis

In order to simulate resistive gate transistors, a one‐dimensional simulator, which permits the use of multiple gate contacts on the transistor structure, has been developed. In…

Abstract

In order to simulate resistive gate transistors, a one‐dimensional simulator, which permits the use of multiple gate contacts on the transistor structure, has been developed. In the case of the multiple gate contact resistive gate transistor, there is a voltage gradient in the gate. The gate voltage thus varies at each point in the channel of the transistor. A gate structure was designed with a geometric profile that gave either a decreasing or an increasing electric field in the gate, depending on the differential voltage applied to the gate contacts. In the saturation region, this parabolically shaped gate structure resulted in a linear relationship between the drain current and the differential gate voltage or gate current. A significant result obtained was the reversal of the drift current direction at certain bias levels. It was also found that the diffusion current may dominate in the strong inversion region of the channel of an NMOS transistor with a resistive gate.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 12 no. 4
Type: Research Article
ISSN: 0332-1649

1 – 10 of 198