LATERAL GATE BIAS EFFECTS IN RESISTIVE GATE NMOS TRANSISTORS

Abstract

In order to simulate resistive gate transistors, a one‐dimensional simulator, which permits the use of multiple gate contacts on the transistor structure, has been developed. In the case of the multiple gate contact resistive gate transistor, there is a voltage gradient in the gate. The gate voltage thus varies at each point in the channel of the transistor. A gate structure was designed with a geometric profile that gave either a decreasing or an increasing electric field in the gate, depending on the differential voltage applied to the gate contacts. In the saturation region, this parabolically shaped gate structure resulted in a linear relationship between the drain current and the differential gate voltage or gate current. A significant result obtained was the reversal of the drift current direction at certain bias levels. It was also found that the diffusion current may dominate in the strong inversion region of the channel of an NMOS transistor with a resistive gate.

Citation

Schieke, P. and du Plessis, M. (1993), "LATERAL GATE BIAS EFFECTS IN RESISTIVE GATE NMOS TRANSISTORS", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 12 No. 4, pp. 341-351. https://doi.org/10.1108/eb051809