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Describes a new approach to fast layered manufacturing. The improvements in speed are achieved entirely through software control of existing commercial layered manufacturing equipment. In particular, the exterior regions of a part are built with thin layers to provide a precise, smooth exterior surface, while its interior regions are built with fast, thick layers to reduce overall build time. This approach has been implemented and tested with .STL CAD models on a Stratasys FDM 1600 rapid prototyping system, where a 50‐80 per cent reduction in build time of dense parts has been achieved without reducing surface quality or part integrity.

Various thick film varistor constructions were made and characterised: ‘sandwich’, ‘interdigitated’ and ‘segmented’ varistors. The varistor active layer thickness, the electrode surface value and shape were varied. The Ul characteristics of these varistors were compared mutually, and with the Ul characteristics of the smallest chip varistors. In accordance with the results obtained, it has been shown that thick film printed varistors composed of ZnO and with additives could be applied as discrete components or integrated into a hybrid circuit.

A variety of thick film planar inductors, designed for applications in the HF range, were printed from conductive PdAg and NiFe₂O₄ ferrite paste on alumina substrate. Pure ferrite powder with a nanometric particle size was used in the NiFe₂O₄ paste preparation. The ferrite thick film layer characterisation was performed on small spirals, after which the following inductor planar geometries were tested together with ferrite layers: meanders, spirals, bispirals and solenoid in plane. Their impedance was analysed with an impedance analyser in the MHz‐GHz range. The results obtained were compared with the properties of the smallest cubic inductors and with the literature data for planar inductors (theoretical and practical). A comparison was made of the L geometries printed. It was observed that better utilisation of the thick ferrite layers was achieved on L geometries with equally distributed windings over the thick ferrite layers.

An overview has been presented on the topic of alternative surface finishes for package I/Os and circuit board features. Aspects of processability and solder joint reliability were described for the following coatings: baseline hot‐dipped, plated, and plated‐and‐fused 100Sn and Sn‐Pb coatings; Ni/Au; Pd, Ni/Pd, and Ni/Pd/Au finishes; and the recently marketed immersion Ag coatings. The Ni/Au coatings appear to provide the all‐around best options in terms of solderability protection and wire bondability. Nickel/Pd finishes offer a slightly reduced level of performance in these areas which is most likely due to variable Pd surface conditions. It is necessary to minimize dissolved Au or Pd contents in the solder material to prevent solder joint embrittlement. Ancillary aspects that include thickness measurement techniques; the importance of finish compatibility with conformal coatings and conductive adhesives; and the need for alternative finishes for the processing of non‐Pb bearing solders are discussed.

Plastic ball grid array packages were aged for up to 2000 hours. Various solder ball pad metallurgies were studied and solder ball shear tests were conducted at a range of ageing times. The solder ball shear strength was found to decrease after an initial hardening stage. The deterioration of solder ball shear strength was found to be mainly caused by the formation of intermetallic compound layers, together with microstructural coarsening and diffusion related porosity at the interface. For the ball pad metallurgy, two distinct intermetallic compound layer structures were observed to have formed after ageing. Once two continuous intermetallic compound layers formed fracture tended to occur at their interface. For the ball pad metallurgies which do not form two continuous intermetallic compound layers, the shear strength still decreased, due to the coarsening of the microstructure, intermetallic particle formation and diffusion related porosity at the surface of the Ni₃Sn₄.

The purpose of the paper is to show up the current possibilities by combination of classic thick-film technology with advanced processing. Thick-film hybrid ceramic substrates have been a base for highly reliable devices for space, aerospace, medical and industrial applications since many years. The combination of classic thick-film printing with advanced technologies for fine line structuring provides substrates best suited for packaging solutions with challenging requirements, such as temperature stability and extended product lifetime. Combined with state of the art assembly technologies, thick-film substrates are used in highly demanding industries.

In recent years, several technologies for fine line structuring have been introduced, e.g. fine line printing, photo imaging, etching, laser structuring for local chip fan-out or fine line structuring on single layers. For further miniaturization of thick-film multilayers circuits, after solving the fine line resolution, the reduction of electrical connection of conductive layers through printed insulation/dielectric layer (via) diameters to connect the layers should be addressed.

The focus of this paper is to show the results of combining fine line structuring with laser microvias and to compare laser drilling in thick-films with different established via forming technologies.

The reduction of via size to 60 µm – smaller than 50% compared to using state-of-the-art printing technologies enables a solution for significant relaxation of current design possibilities.

Coating and lithography steps in thin‐film processing require planar and smooth surfaces. Usually ceramic substrates with as‐fired surface roughness of R_a < 0.1µm or with polished surfaces for advanced requirements are used. In general, a thick‐film hybrid has an inappropriate surface for further successful thin‐film processing. In this work, the influence of surface roughness and topography on the properties of thin‐film conductors and the fabrication of vias is investigated. Surface smoothing and local planarisation can be achieved by the use of a thick‐film overglaze or by coating the surface with polyimide prior to thin‐film processing. The improvements in conductor and via yield are measured by adequate test structures with a conductor width of 25µm. Based on the results, a process is given to provide a thick‐film multilayer with a sufficient smooth and planar surface suitable for thin‐film processes.

Presents the results of a study of the effects of solder ball pad metallurgy, intermetallic compound (IMC) thickness and thermal cycling on the shear strengths of PBGA package solder balls. The study of the microstructures of solder balls revealed that only a very thin layer of intermetallic compound existed between solder balls and Ni or Ni alloy barrier layers immediately after ball placement and reflow. The protective Au layer was dissolved completely and a needle like AuSn₄ intermetallic compound was then formed and dispersed evenly in the solder balls. The overall thickness of the IMC layers was thicker than 15μm after storage at 150°C for 1,000 hours. During the shear tests failure occurred at the interface of the two IMC layers. The fracture surfaces of solder balls with electrolytic Ni and thick Au layers were smooth and brittle fracture was observed. The ball shear strength decreased dramatically with the formation of IMC layers. For the solder balls with electroless Ni and thin Au layers, only a single IMC layer was formed at the interface and its thickness was only 2.5 μm after storage at 150°C for 1,000 hours.

The purpose of this article is the effect of doping minor Ni on the microstructure evolution of a Sn-xNi (x = 0, 0.05 and 0.1 wt.%)/Ni (Poly-crystal/Single-crystal abbreviated as PC Ni/SC Ni) solder joint during reflow and aging treatment. Results showed that the intermetallic compounds (IMCs) of the interfacial layer of Sn-xNi/PC Ni joints were Ni₃Sn₄ phase, while the IMCs of Sn-xNi/SC Ni joints were NiSn₄ phase. After the reflow process and thermal aging of different joints, the growth behavior of interfacial layer was different due to the different mechanism of element diffusion of the two substrates. The PC Ni substrate mainly provided Ni atoms through grain boundary diffusion. The Ni₃Sn₄ phase of the Sn0.05Ni/PC Ni joint was finer, and the diffusion flux of Sn and Ni elements increased, so the Ni₃Sn₄ layer of this joint was the thickest. The SC Ni substrate mainly provided Ni atoms through the lattice diffusion. The Sn0.1Ni/SC Ni joint increases the number of Ni atoms at the interface due to the doping of 0.1Ni (wt.%) elements, so the joint had the thickest NiSn₄ layer.

The effects of doping minor Ni on the microstructure evolution of an Sn-xNi (x = 0, 0.05 and 0.1 Wt.%)/Ni (Poly-crystal/Single-crystal abbreviated as PC Ni/SC Ni) solder joint during reflow and aging treatment was investigated in this study.

Results showed that the intermetallic compounds (IMCs) of the interfacial layer of Sn-xNi/PC Ni joints were Ni₃Sn₄ phase, while the IMCs of Sn-xNi/SC Ni joints were NiSn₄ phase. After the reflow process and thermal aging of different joints, the growth behavior of the interfacial layer was different due to the different mechanisms of element diffusion of the two substrates.

In this study, the effect of doping Ni on the growth and formation mechanism of IMCs of the Sn-xNi/Ni (single-crystal) solder joints (x = 0, 0.05 and 0.1 Wt.%) was investigated.

The trend in wireless and mobile communications for broader bandwidth microwave circuitry, coupled with high packaging density and low cost fabrication has triggered investigations of new circuit configurations and technologies that meet these requirements. We have addressed these issues through the study of multilayer microwave structures using advanced thick‐film technology. The techniques described employ several layers of metal sandwiched by thick‐film dielectric. This leads to an efficient solution for system miniaturisation. The significance of this work is that it shows the multilayer approach to microwave structures, coupled with new thick‐film technology, offers a viable and economic solution to achieve high‐density, high‐performance microwave circuits.