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Coating and lithography steps in thin‐film processing require planar and smooth surfaces. Usually ceramic substrates with as‐fired surface roughness of R_a < 0.1µm or with polished surfaces for advanced requirements are used. In general, a thick‐film hybrid has an inappropriate surface for further successful thin‐film processing. In this work, the influence of surface roughness and topography on the properties of thin‐film conductors and the fabrication of vias is investigated. Surface smoothing and local planarisation can be achieved by the use of a thick‐film overglaze or by coating the surface with polyimide prior to thin‐film processing. The improvements in conductor and via yield are measured by adequate test structures with a conductor width of 25µm. Based on the results, a process is given to provide a thick‐film multilayer with a sufficient smooth and planar surface suitable for thin‐film processes.

During the thermal processing of thin films in which low intensity line heat sources are used, extended processing times are often required to reach steady state (˜15 sec). In addition, the melting of the film may occur some time after processing has begun, and therefore there is no initial melting condition within the film. In such cases, computer simulations may become very time consuming, and the development of an efficient computational method which incorporates the initial formation of the melt during processing is necessary. A general technique was developed to accurately model two‐dimensional heat conduction in a multilayer film structure with one‐dimensional phase change in one of the thin films. These conditions frequently exist in thin film thermal processing when the thermal gradient through the thickness of the melting film can be considered negligible. The method involves an implicit formulation of the modified enthalpy method. The solid/liquid interface energy‐balance equation is taken into account which allows the exact location of the interface to be tracked within a control volume. A comparison is made between the explicit and implicit modified methods to test efficiency and accuracy. The implicit method is then applied to the zone‐melting recrystallization of a silicon thin film in a multilayer structure.

A novel interconnect technology, introducing thin film on a laminate substrate base, is presented. A specially constructed laminate board is used as a substrate for the thin film build‐up process. The main characteristics of the laminate core substrate are the z‐axis electrical connections, the absence of holes in the substrate and the very flat nature of the top surface. As a result, the base substrate can be processed further in a thin film processing line. The manufacturing and properties of these substrates are discussed.

Polymer-based thermal interface materials (TIMs) are having pump out problem and could be resolved for reliable application. Solid-based interface materials have been suggested and reported. The purpose of this paper is suggesting thin film-based TIM to sustain the light-emiting diode (LED) performance and electronic device miniaturization.

Consequently, ZnO thin film at various thicknesses was prepared by chemical vapour deposition (CVD) method and tested their thermal behaviour using thermal transient analysis as solid TIM for high-power LED.

Low value in total thermal resistance (R_th-tot) was observed for ZnO thin film boundary condition than bare Al boundary condition. The measured interface (ZnO thin film) resistance {(R_th-bhs) thermal resistance of the interface layer (thin film) placed between metal core printed circuit board (MCPCB) board and Al substrates} was nearly equal to Ag paste boundary condition and showed low values for ZnO film prepared at 30 min process time measured at 700 mA. The T_J value of LED mounted on ZnO thin film (prepared at 30 min.) coated Al substrates was measured to be 74.8°C. High value in junction temperature difference (ΔT_J) of about 4.7°C was noticed with 30 min processed ZnO thin film when compared with Al boundary condition. Low correlated colour temperature and high luminous flux values of tested LED were also observed with ZnO thin film boundary condition (processed at 30 min) compared with both Al substrate and Ag paste boundary condition.

Overall, 30 min CVD processed ZnO thin film would be an alternative for commercial TIM to achieve efficient thermal management. This will increase the life span of the LED as the proposed material decreases the T_J values.

Dr Setty reports from ISHM‐India, who had their first committee meeting on the 4th October 1985, that the Society is now off the ground and that the Symposium on Hybrid Microelectronics held on February 5th attracted considerable interest, some 150 persons attending. Dr Sonde was the organising committee Chairman and was fortunate in being able to persuade the Department of Electrical Communication Engineering of the Indian Institute of Science in Bangalore, which has set up its thin and thick film hybrid department, to host this important event. Papers were given by visiting speakers from the US, UK and West Germany as well as from India itself. Among the presentations given were papers introducing some of the country's facilities from which it can be seen that microelectronics has an important future here.

The purpose of this paper is to investigate damaging processes in TaN thin film absorbers under action of high-voltage electrical pulse of nanosecond duration. Despite having mechanical origin of crack opening, estimation based on the readings from oscillograms shows uncharacteristically high velocities of the crack propagation.

Microscopic images of damaged absorbers showing the final result of the damaging process provided initial information about its geometrical peculiarities. Then, to clarify the dynamics of the process, the authors create the model of the crack, having elements of self-similarities and multiple stage opening. The influence of heating induced by current concentration at crack tip and of magnetic stress of this concentrated current are both included in the model.

Using physical parameters of TaN layers with flowing current and performing calculations the authors define the conditions required to initiate the damaging process and to sustain it. Danger of such damage is relevant for high-T_c superconducting thin films after their switching to normal state which is induced by the high-voltage pulse.

There were made recommendations to manufactures aiming to improve electrical durability of the absorbers in an effort to prevent the damaging influence of power nanosecond electrical pulses.

Three stage opening model implies the appearance of zone of high-energy dissipation that can lead to detonation-like destruction of the film and, therefore, explain the high velocities of crack propagation.

For TAB tapes and flex circuitry, laminates with adhesives (3‐layer laminates) are commonly used. The drawbacks of adhesives are well known. Adhesiveless flexible copper‐polyimide laminates (2‐layer laminates) could avoid such disadvantages. Two‐layer thin film laminates may be produced using sputtering technology. Good adhesion strength between the copper and the polyimide film may be achieved by means of special plasma treatment. The advantages and disadvantages of 2‐layer flexible thin film laminates are discussed in this paper, along with their different production methods. The adhesion strength of 2‐layer laminates in comparison with 3‐layer laminates will be pointed out. Future uses of 2‐layer flexible thin film laminates will be considered, along with their benefits.

Material formulation, structuring and modification are key to increasing the unit volume complexity and density of next generation electronic packaging products. Laser processing is finding an increasing number of applications in the fabrication of these advanced microelectronic devices. The purpose of this paper is to discuss the development of new laser‐processing capabilities involving the synthesis and optimization of materials for tunable device applications.

The paper focuses on the application of laser processing to two specific material areas, namely thin films and nanocomposite films. The examples include BaTiO₃‐based thin films and BaTiO₃ polymer‐based nanocomposites.

A variety of new regular and random 3D surface patterns are highlighted. A frequency‐tripled Nd:YAG laser operating at a wavelength of 355 nm is used for the micromachining study. The micromachining is used to make various patterned surface morphologies. Depending on the laser fluence used, one can form a “wavy,” random 3D structure, or an array of regular 3D patterns. Furthermore, the laser was used to generate free‐standing nano and micro particles from thin film surfaces. In the case of BaTiO₃ polymer‐based nanocomposites, micromachining is used to generate arrays of variable‐thickness capacitors. The resultant thickness of the capacitors depends on the number of laser pulses applied. Micromachining is also used to make long, deep, multiple channels in capacitance layers. When these channels are filled with metal, the spacings between two metallized channels acted as individual vertical capacitors, and parallel connection eventually produce vertical multilayer capacitors. For a given volume of capacitor material, theoretical capacitance calculations are made for variable channel widths and spacings. For comparison, calculations are also made for a “normal” capacitor, that is, a horizontal capacitor having a single pair of electrodes.

This technique can be used to prepare capacitors of various thicknesses from the same capacitance layer, and ultimately can produce variable capacitance density, or a library of capacitors. The process is also capable of making vertical 3D multilayer embedded capacitors from a single capacitance layer. The capacitance benefit of the vertical multilayer capacitors is more pronounced for thicker capacitance layers. The application of a laser processing approach can greatly enhance the utility and optimization of new materials and the devices formed from them.

Laser micromaching technology is developed to fabricate several new structures. It is possible to synthesize nano and micro particles from thin film surfaces. Laser micromachining can produce a variety of random, as well as regular, 3D patterns. As the demand grows for complex multifunctional embedded components for advanced organic packaging, laser micromachining will continue to provide unique opportunities.

The purpose of this paper is to present the utilities of packaging and PCB fabrication processes for manufacturing micro electromechanical systems (MEMS) and its package for sensing and actuation applications.

A broad array of manufacturing approaches available in the packaging industry, including lamination, lithography, etching, electroforming, machining, bonding, etc. and a large number of available functional materials such as polymers, ceramics, metals, etc. were explored for producing functional microdevices with greater design freedom.

Good quality MEMS devices can be manufactured using packaging style fabrication, particularly using stacks of laminates. Furthermore, such microdevices can be built with a high degree of integration, pre‐packaged, and at low cost.

Further manufacturing research work should be undertaken in collaboration with the PCB and packaging industries, which stand to benefit greatly by expanding their offerings beyond serving the semiconductor industry and developing their own integrated MEMS products.

The paper presents examples of basic packaging fabrication processes for producing 3‐D structures and free‐standing structures, and a new MEMS manufacturing paradigm to build micro‐electromechanical (MEMS) for biomedical, optical, and RF communication applications.

The Hybrid Microelectronics Laboratory in the Bradley Department of Electrical Engineering at Virginia Polytechnic Institute and State University (VPI & SU), also named Virginia Tech, was established during the 1979–1980 academic year in order to provide classroom/laboratory instruction and research capabilities in the area of hybrid microelectronics. The laboratory was initially designed for the hybrid and thick film areas of microelectronics. Thin film design and fabrication capability was added in the Fall Semester, 1987. Currently, efforts are under way to develop the area of monolithic diffusion and processing of semiconductor wafers using both elemental and compound materials, initiated in the Fall Semester, 1991.