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This paper discusses how the grain size of plated copper changes as time passes by observing the copper surface topography after surface treatment with a roughening agent. This paper also discusses how the time until the recrystallization terminates depends on the amount and type of plating additives as well as current density. The results agree with the known mechanism of grain growth. As a result of our experiments, the best process to gain the optimal surface topography is proposed. We firmly believe that this paper will contribute to the improvement in quality control of the copper surface treatment process, which will in turn lead to the fabrication of PCBs and plastic packages with higher reliability.

Copper electrodeposition acts as a crucial step in the manufacture of high-density interconnect board. The stability of plating solution and the uniformity of copper electrodeposit are the hotspot and difficulty for the research of electrodeposition. Because a large number of factors are included in electrodeposition, experimentally determining all parameters and electrodeposition conditions becomes unmanageable. Therefore, a multiphysics coupling technology was introduced to investigate microvia filling process, and the mechanism of copper electrodeposition was analyzed. The results provide a strong theoretical basis and technical guidance for the actual electroplating experiments. The purpose of this paper is to provide an excellent tool for quickly and cheaply studying the process behavior of copper electrodeposition without actually needing to execute time-consuming and costly experiments.

The interactions among additives used in acidic copper plating solution for microvia filling and the effect on the copper deposition potential were characterized through galvanostatic measurement (GM). The adsorption behavior and surface coverage of additives with various concentrations under different rotating speeds of working electrode were investigated using cyclic voltammetry (CV) measurements. Further, a microvia filling model was constructed using multiphysics coupling technology based on the finite element method.

GM tests showed that accelerator, inhibitor and leveler affected the potential of copper electrodeposition, and bis(3-sulfopropyl) disulfide (SPS), ethylene oxide-propylene oxide (EO/PO) co-polymer, and self-made leveler were the effective additives in acidic copper plating solution. CV tests showed that EO/PO–Cu⁺-Cl⁻ complex was adsorbed on the electrode surface by intermolecular forces, thus inhibiting copper electrodeposition. Numerical simulation indicated that the process of microvia filling included initial growth period, the outbreak period and the stable growth period, and modeling result was compared with the measured data, and a good agreement was observed.

The research is still in progress with the development of high-performance computers.

A multiphysics coupling platform is an excellent tool for quickly and cheaply studying the electrodeposited process behaviors under a variety of operating conditions.

The numerical simulation method has laid the foundation for mechanism of copper electrodeposition.

By using multiphysics coupling technology, the authors built a bridge between theoretical and experimental study for microvia filling. This method can help explain the mechanism of copper electrodeposition.

This study aims to understand the influence of megasonic (MS)-assisted agitation on printed circuit boards (PCBs) electroplated using copper (Cu) electrolyte solutions to improve plating efficiencies through enhanced ion transportation.

The impact of MS-assisted agitation on topographical properties of the electroplated surfaces was studied through a design of experiments by measuring surface roughness, which is characterised by values of the parameter Ra as measured by white light phase shifting interferometry and high-resolution scanning electron microscopy.

An increase in Ra from 400 to 760 nm after plating was recorded for an increase in acoustic power from 45 to 450 W. Roughening increased because of micro-bubble cavitation energy and was supported through direct imaging of the cavitation. Current thieving effect by the MS transducer induced low currents, leading to large Cu grain frosting and reduction in the board quality. Current thieving was negated in plating trials through specific placement of transducer. Wavy electroplated surfaces, due to surface acoustic waves, were also observed to reduce the uniformity of the deposit.

The formation of unstable transient cavitation and variation of the topology of the Cu surface are unwanted phenomena. Further plating studies using MS agitation are needed, along with fundamental simulations, to determine how the effects can be reduced or prevented.

This study can help identify manufacturing settings required for high-quality MS-assisted plating and promote areas for further investigation, leading to the development of an MS plating manufacturing technique.

This study quantifies the topographical changes to a PCB surface in response to MS agitation and evidence for deposited Cu artefacts due to acoustic effects.

The adsorption and acceleration behavior of 3-mercaptopropyl sulfonate (MPS) were investigated by electrochemical tests for microvia filling by copper electroplating.

The synergistic effects of one suppressor of propylene oxide ethylene oxide propylene oxide named PEP and MPS as the accelerator during copper electroplating were also investigated by electrochemical methods such as electrochemical impedance spectroscopy cyclic voltammetric stripping (CVS) and Galvanostatic measurements (GMs).

The research results suggest that the adsorption of MPS onto the Cu-RDE metal surface was a spontaneous process and the adsorbing of MPS on cathode was proposed to physical-chemistry adsorption in the plating formula. There was no potential difference (i.e. ?? = 0) of GMs until MPS was injected into the plating solution suggest that copper deposition is not diffusion-controlled in the presence of PEP–Cl–JGB.

A new composition of plating bath was found to be effective to perform bottom-up copper filling of microvias in the fabrication of PCB in electronic industries. The adsorption of MPS into the Cu-RDE metal surface was a spontaneous process and the adsorbing of MPS on cathode was studied by EIS and the results proposed to physical-chemistry adsorption in the plating formula. An optimal plating solution composed of CuSO4, H2SO4, chloride ions, PEP, MPS and JGB was obtained, and the microvia could be fully filled using the plating formula.

Insoluble and therefore oxygen developing anodes tend to destroy additives in plating baths. With a modified mixed metal oxide coated anode, it is possible to reduce the consumption of additives in copper electrolytes and to reduce the formation of Sn⁴⁺ in acid tin electrolytes. Favourable applications for this new anode type are under discussion.

Driven by the demand for higher density in electronic packaging, each signal plane of printed wiring board must accommodate more conductors. As a result, conductor width is becoming narrower each year. This chapter reviews some of the important steps of forming finer line conductors in printed wiring boards, such as surface preparation, plating/etching, photo‐exposure, automatic optical inspection, etc.

The purpose of this paper is to present new developments in electrolytic tin plating designed to eliminate the formation of whiskers over time, when tin is plated on copper.

Two main approaches were undertaken to achieve the desired results. The first was modification of the copper substrate prior to plating and the second was to modify the crystal structure of the tin deposit.

With the use of specific additives to the tin plating bath it was possible to achieve a crystal structure similar to that of the non‐whiskering tin/lead.

The technology is presently available commercially to plate electronic parts such as connectors and lead frames, etc.

The paper details a modified electroplating tin bath that produces a deposit that will not form whiskers over time.

Moulded substrates offer a wide spectrum of performance at economical prices, featuring enhanced electrical, physical and environmental properties. By expanding interconnection into a third dimension by providing connectivity between or along non‐planar surfaces or planes, moulded boards allow designers the freedom to be highly creative in devising circuitry comprising complex shapes or forms of unique sculpture. Opportunities abound for achieving cost reductions, savings being achieved first through eliminating processing steps in PCB fabrication and secondly by simplifying or minimising sub‐assembly or final assembly labour or hardware costs. In addition, further savings can be achieved by incorporating attachment joining techniques like ultrasonic welding. Discussion covers the characteristics of moulded substrates, metallisation of unclad substrates using the additive process, and several applications of moulded circuitry and 3‐D assemblies, before a prediction of the future potential for this technology.

An IC manufacturer's experience with a new technology for connecting bare chips to flexible PCBs is described. The process produces low‐cost fine line flexible PCBs and also direct chip to PCB connection as an integral step in PCB production. The paper is addressed to managers and technologists involved in MCM or bare chip packaging development and fabrication. The technology described was developed by AMEG in conjunction with a number of specialist companies and presents an approach of strategic significance to the industry. IC (integrated circuit) packaging technology is a priority issue, as systems' performance is no longer silicon driven, but is now determined by the interconnection systems used between ICs. This problem is not new, but is rapidly escalating. There is an abundance of technical offerings addressing this question. However, those capable of acceptable performance are distinguished by their high level of both complexity and cost. Of greater consequence is their inability to be effectively implemented in the ‘real world’. One IC house has identified this as a key strategic issue. It accepts that a solution must also make managerial sense, consider the logistics issues, be cost‐effective and enable a practical implementation strategy. The results of this development are the subject of this paper. Despite its divergent development terms of reference, technical performance is not compromised.