Electronic Circuits World Convention 10 (ECWC 10) 2005

Citation

Goosey, M. (2005), "Electronic Circuits World Convention 10 (ECWC 10) 2005", Circuit World, Vol. 31 No. 4. https://doi.org/10.1108/cw.2005.21731dac.002

Electronic Circuits World Convention 10 (ECWC 10) 2005

Electronic Circuits World Convention 10 (ECWC 10) 2005

Keywords: Conventions, Electronic industry

From Sunday, 20 February 2005, the Anaheim Convention Center in California (Plates 1 and 2) hosted the IPC Circuits Expo/APEX, a Designers' Summit and the Electronic Circuits World Convention 10. The ECWC 10 took place from Tuesday 22 to Thursday 24 February and there were many parallel technical sessions running during the three days of the convention. Consequently, this report merely gives an overview of some of the key papers presented. For those wishing to have more comprehensive information on the overall programme and more specific details of the individual papers, a CD- ROM of the proceedings is available from the IPC (www.ipc.org).

Plate 1 Anaheim Convention Center

The opening keynote presentation was given by Michael Marks, the CEO of Flextronics. Michael gave an overview of the growth of Flextronics and he described how it would be an $18 billion company by next year. He explained how the company had shown continued revenue growth, although profitability had sometimes been elusive in recent years. The capital intensive nature of the industry was discussed in the context of the shift in manufacturing centre of gravity to China and the need to extract as much value as possible from the design stage right through to manufacturing. It was predicted that the need for huge capital investment was a barrier to new entry into the sector and the recent consolidation of the industry meant that there were now relatively few global players. Michael also highlighted the significance of the Indian software industry and how Flextronics employed almost 4,000 software engineers in that country. He also suggested, however, that India was unlikely to be a significant place for manufacturing in the near future because of its very poor infrastructure, especially when compared to China.

Plate 2 The opening ceremony

One of the initial technical sessions on Tuesday covered the future of optoelectronics technology and the first paper from Toru Nakashiba et al. of Matsushita Electric Works in Osaka, Japan, detailed their investigations of optical couplers made using embedded micro-mirrors on optical wiring boards. Micro-mirrors were fabricated using either an etching method or a moulding method. The final target of this work was to produce low-cost optical wiring boards that were compatible with conventional printed wiring boards. The fabrication process of the optical wiring board was detailed: the base PWB material used was conventional FR4 and the optical waveguide and cladding were also fabricated from an epoxy. The coupling characteristics of the structures produced were reported and data for optical loss, near field and far field patterns and misalignment tolerance were given for experiments carried out using an 850 nm light source. Overall mirror loss was found to be around 0.5 dB/mirror. The conclusion was that the use of embedded micro-mirrors was a promising approach to the provision of low-cost optical wiring boards.

The next paper was given by James Howard of WUS Printed Circuits and this was entitled “Printed circuit board architecture for the use of optical interconnection components”. The presentation reviewed current device placement methodologies and the limitations of this technology for on- board transmission of signals in terms of size, surface space requirements and limited channel availability. A model using an interposer was suggested as an approach for reducing surface space and communication time between elements. Overall, the paper presented a simple architecture for an optical PCB which permitted manufacturing with the materials used in standard PCB fabrication. The basic concept was that very short distances of z-axis travel within a PCB can best be achieved electrically, allowing the surface devices and general layout to be nearly standard and to use inexpensive devices. The internal transmission of optical signals is done only within a plane, making the manufacturing much easier and the reliability as good as other embedded device PCBs. This approach was predicted to enable a much less expensive optical PCB to be fabricated.

The next paper was given by Tatiana Berdinskikh of Celestica in Toronto, Canada and this paper covered cleanliness specifications for single- mode connectors. The paper detailed work carried out by seven companies including Alcatel and Tyco and it summarized the results of over 212 years of effort which has now been adopted as the draft IPC cleanliness standard 8497. The objective was to develop basic test and measurement procedures based on quantitative data.

The final paper of this session reported the results of a NEMI cost analysis project which compared optical and copper backplanes and it was given by Adam Singer of Cookson Electronics in Foxborough, Massachusetts. Over 30 people had contributed to the work that was reported in this paper. As the performance of copper interconnects had been stretched to between 10 and 40 Gb/s, the costs required to achieve this enhanced performance had also increased. At some point there comes a switch over point where optical interconnection is better. There were various estimates of how far copper interconnects can be pushed and these vary up to as high as 40 Gb/s, depending on a number of factors. Copper is also limited in bandwidth due to increasing skin effects at higher frequencies. Photons were claimed to be best for long distance high speed signal transmission while electrons were better for transmission over shorter distances, i.e. <5 m and at moderate to high speeds. Some of the areas this group had addressed included manufacturability of waveguides and their integration into PWBs. The conclusion from this work was that the NEMI optical backplane cost modelling team had developed the framework for comparing optical PCBs to today's copper PCBs. PCB fabricators and OEM users had validated the copper case output costs thus ensuring that the model was within 10 per cent of their internal cost models.

Session S06 had a focus on “Advanced Packaging Technology” and there were three papers covering various aspects of this interesting topic. The first paper was given by Koichi Nakayama and covered the development of high-density wiring technology and interconnect technology with silicon through-holes. The process described used 6in. silicon wafers and the use of reactive ion etching to form deep vias. The vias formed were filled with copper by plating or paste filling and then the back of the wafer was ground away to open up the vias to form holes. Through hole diameters of 10-300 μm had been produced and aspect ratios up to 17 had been achieved. The breakdown voltage of the through holes was found to be .400 V. The plating of the high aspect ratio vias was optimised by control of the plating chemistry additives. An additive plating method was also developed in which plating was performed after the vias had been converted to holes by back grinding. Reliability assessments using daisy chain structures exposed to thermal humidity bias testing highlighted the importance of a TiN barrier layer film before copper deposition. Thermal cycling tests gave a similar indication that the use of TiN enhanced reliability. The presentation then went on to discuss the development of a fine wiring process using sputtered metals on a benzocyclobutene (BCB) film on silicon. If a thin (30 nm) chromium or titanium seed layer was deposited on the BCB before a 200nm copper film was deposited the adhesion was significantly improved. Wiring was produced with 5 μm lines and spaces and via/land dimensions of 20/30 mm, respectively.

Toshihisa Kumakura of the Hitachi Chemical Company, Shimodate-shi, Ibaraki, Japan, then presented a paper entitled “Insulation material for next generation packaging substrates”. He began by outlining the required specifications for packaging and the trend towards greater miniaturisation and how this had influenced the types of packing being used. He showed trends in pitch reductions, number of I/Os and operating frequency requirements and how these were driving the need for new packaging materials. In particular, a conceptual model for new types of dielectric resins was described which included the development of a new epoxy resin matrix material, a new hardener chemistry and a surface treated filler. Although details of the chemistry were proprietary, the physical properties of an example material were described in detail. It had good peel strength even with a low surface profile, high elongation, low Dk and Df at high frequency and it was claimed to be environmentally friendly. The thermal expansion coefficient up to 100°C was quoted as being 44 ppm/K. The new material was much less attacked by the desmear chemistry and the resulting low surface profile helped to improve transmission loss, especially at high frequencies. Thermal cycling and solder shock testing had been used to investigate crack development and electrical reliability had been evaluated using temperature, humidity, bias, testing.

The final paper of this session was given by Robert Turunen of DKN Research, Haverhill, Massachusetts and it covered micro-bump array constructions on organic substrates for non-permanent terminations. A series of electroless and electroplating processes that had originally been used to build various kinds of micro-bump arrays on copper pads on organic substrates had been developed for non-permanent connections. Many kinds of bump shapes had been prepared by using combinations of photoimaging, plating and plasma etching with various copper foundation structures. Non-permanent bumps were said to be needed to provide certain types of high density terminations. They could also be made using screen printing and chemical etching as well as by plating. Various materials including tin-lead solder, copper, nickel-gold, tin, silver and lead-free solder were possible bump materials. Pitches of less than 50 μm had been produced and the use of a copper seed layer on top of the existing copper layer gave higher mechanical reliability.

Not surprisingly, there were several sessions dedicated to the increasingly important topic of lead-free assembly and Tuesday afternoon concluded with an extremely well attended free workshop on lead-free solder reliability which was run by Dr Jon Lau of Agilent Technologies. There were three presentations in this session and two of them focused on the use of low temperature lead-free solders and the reliability performance that could be expected. Jerry Gleason of Hewlett Packard detailed work on the design, materials and assembly processes for high density packages with a tin- bismuth-silver (Sn-Bi-Ag) alloy that had a melting point of 139°C. Various topics were covered including the potential for cost reductions and other benefits that could be achieved using this alloy. A large amount of supporting data was presented and it was concluded that the Sn-Bi-Ag alloy could indeed be a viable alternative to lead-free alloy for printed circuit assembly applications having temperature constraints that prevented the use of Sn-Ag-Cu. The assembly process for Sn-Bi-Ag lead-free test boards was very robust and assembly yields of almost 100 per cent could be achieved.

The second paper of the workshop was given by Sammy Shina from the University of Massachusetts and in this he detailed the reliability testing results obtained from a surface mount lead-free soldering material and process evaluation that had been carried out by a consortium based in New England. Several combinations of solderable finish, solder paste and atmosphere had been used in a test matrix and pull test data was reported as one metric for evaluating solder joint reliability. He recommended visiting the web site of the Massachusetts Toxic Use Reduction Institute (www.turi.org) for additional information on their work.

The session concluded with an interesting presentation from Jon Lau which detailed basic reliability theory before focusing on the reliability testing and failure analysis of high density packages assembled with the Sn-Bi-Ag alloy. There were significant differences found depending on the type of package format being evaluated, sometimes the lead-free devices were better and sometimes those containing lead-based solder were best. There was then a discussion of what accelerated testing data meant in terms of real-life applications and it was concluded that it was not yet possible to translate accelerated testing data to actual field service predictions with any degree of certainty.

On Wednesday morning the convention began with a keynote speech from Walt Custer of Custer Consulting in which he covered the “Business outlook for the global electronics industry”. Walt gave a comprehensive overview of the industry data covering all industry sectors and he used these to give a predictive indication of business conditions for the rest of 2005 and beyond. He highlighted the effect of the weakening dollar against the euro; the dollar had weakened by 48 per cent against the euro. Because the Chinese Yuan was tied to the dollar, this meant that Chinese exports to Europe were now effectively 48 per cent cheaper. Walt also emphasized the seasonality of the industry where there was a large upward blip in sales during the last quarter of each year. A good indicator of the move of electronics assembly to the Far East was shown by the big growth in semiconductor sales to Asia, which has largely been at the expense of the US industry. Focusing on PCB production it was stated that global PCB production had been valued at $38.08 billion in 2004. More than 75 per cent of these boards were made in the Far East, while European production was now less than 10 per cent. Interestingly, the world's five largest PCB companies were all Japanese. AT&S was the biggest European PCB fabricator but most of its activity was in the Far East and it had announced additional expansions in Russia and Japan for 2005. For the electronics industry as a whole, Walt suggested that overall growth would be slowed by increasing interest rates, but growth of 6.8 per cent was still expected globally for all electronics production. The prediction for global PCB production for 2005 was $40.8 billion, which was 7 per cent up on the 2004 figure.

There then followed another series of parallel technical sessions. Session S14 was entitled “Printed Board Design for Advanced Packaging” and it was chaired by Paul Waldner of Multiline International Europe. The first presentation was given by Feling Boisen of Texas Instruments, Aalborg, Denmark and was on “Reference Designs, leading PWB fabricators to Future Technology”. The aim of the presentation was to highlight the influence of the key developmental factors and issues on the roadmaps of the leading PCB fabricators. He began by showing the predicted reductions in feature sizes for PCBs out to the year 2010. Microvia production was introduced and issues around filling, aspect ratios, hole diameters, stacking/ staggering and the nature of the base copper were discussed in terms of the challenges in going to smaller dimensions. Predicted trends for feature size reductions in line widths, spaces and via dimensions were given. There would be a move from two stacked vias to three stacked vias in the near future. In order to keep costs down there would be demands on the choice of substrates used and there was likely to be growing use of laser drillable FR4 type materials. The move to lead- free and halogen-free laminates was underway but halogen-free laminates were still relatively expensive and often not yet so readily available. With the move to lead-free it was suggested that solder float testing should be increased to the harsher 288°C for 10 s conditions. It was also emphasised that heavy investments in current technology were delaying the adoption of emerging technologies.

The second presentation was given by Andrew Kowalewski of SyChip Inc, Berowra in Australia and he covered “PCB Design for Flipchip Components”. His company had made extensive use of flipchip technology to enable the production of very small modules and he compared flipchip assembly with the use of conventional packaged devices. Flipchip offered size and weight reductions, gave high packaging density, efficient heat removal and was cheaper in high volumes. Package inductance could be reduced by 98 per cent, capacitance by 70 per cent and resistance by 95 per cent. However, there were also disadvantages, such as the difficulty in rework, the need for high technology, expensive substrates, the fact that some die were light sensitive, and some also needed underfilling, which took time and added cost. Also, not all the required die are always available and thus there may be a need to purchase whole wafers and to use a third party re- bumping service. Flipchip on ceramic is very reliable but on FR4 there is a significant thermal expansion mismatch which reduced reliability. Underfilling and its challenges were also discussed in detail; factors such as the need to leave clearance for the underfill fillet and for the underfill nozzle actually reduced some of the benefits in terms of area reduction. Underfilling large die could be a very slow process and the presence of any voids could reduce reliability. BT based substrates were widely used because they had lower thermal expansions (TCE) and higher Tgs.

Session S17 was on “Advanced Primary Imaging” and it was chaired by Masanari Taniguchi of Tohoku Gakuen University, Japan. The first paper covered the latest technical trends in dry film photoresists and was given by Hiroaki Tomita of Asahi Kasei EMD Corporation, Fuji, Shizuoka, Japan. He detailed a range of resists designed for high resolution, direct imaging and other applications. The key trends in packaging were the move from SOC to SIP, the adoption of semi- additive rather than subtractive interconnect fabrication and the use of direct imaging. Semi-additive processes were much more suitable for producing the 15 μm and below features that were increasingly required. The challenges of producing a super-high resolution dry film resist were detailed; factors such as clean, easy stripping were essential and this had been achieved by using new types of monomers. Laser direct imaging was then discussed and it was stated that it would be especially popular with large size substrates such as these used in flat panel displays. The wavelengths used were typically either 355 or 405 nm and required resist sensitivities that were in the region of 10-50 mJ/cm². Work had been done to develop a new range of high sensitivity sensitiser molecules that gave a narrow grey zone and good resin hardening after a high, but short exposure condition. This was achieved by increasing the double bond density of the resins so that greater crosslinking was achieved. The presentation concluded with a description of an ultrathin (<4 μm) dry film resist for chip on flex and TAB applications, where features of 10-15 μm would be required by 2007. The resists described had a tenting process capability, were semi-additive plating compatible and had been shown to be capable of producing 2 μm lines and spaces.

The next paper covered the development of a dry film photoresist with 15 μm line and space resolution for semi-additive processing and was presented by Hidetaka Uno of DuPont MRC Dry Film Ltd, Utsunomiya, Tochigi, Japan. The paper detailed the technology and approaches necessary to achieve the 25 μm thick, 15 μm lines and spaces that would be needed by 2008 according to the JEITA roadmap. By this time, operating frequencies would be ~6.1 GHz and pin counts per package would be ~4,400. Control of conductor shape at these dimensions would thus be essential in order to maintain signal integrity; this would require the use of a semi-additive patterning process because better conductor shape control was possible. Also, copper surface roughness would need to be reduced because of higher frequency skin effects and this had implications for metal adhesion as there could then be reduced mechanical adhesion. A new dry film resist had been produced to meet these requirements and this had been achieved by careful modification of the resist chemistry.

The final paper of the session was presented by Dr Danny Cheung of Rohm and Haas Electronic Materials, Hong Kong, China and, in contrast to the other two papers, this one detailed the use of liquid resists to achieve high yields and low costs. A brief history of the evolution of liquid resists was presented. Currently, negative aqueous resists had exposure energies of 40 mJ/ cm² and could resolve 25 μm lines and spaces. Liquid resists could be applied using both horizontal and vertical roller coating equipment and the advantages and disadvantages of each technique were discussed; horizontal equipment could process panels as thin as 0.05 μm and as thick as 1.6 μm.

Another popular subject that was addressed several times during the convention was that of embedded components technology and session S21 was a continuation of the morning session on “Embedded Technology”. The session leader was Yoshiyuki Tanaki of DuPont and there were three papers. The first was “Design for Manufacture of Ceramic Thick Film Embedded Capacitors” and this was presented by Bill Borland of DuPont Electronic Technologies, Research Triangle Park, North Carolina, USA. The paper detailed why DuPont had chosen to develop thick film ceramic capacitors for use in conventional PCB substrates. Capacitor arrays were deposited on copper foil and this allowed large numbers to be accommodated in a small space. The dielectric was screen printed on the copper substrate and then a copper top electrode was added before firing at 900°C in a doped N₂ atmosphere. The dielectric was based on barium titanate and a subsequent black oxide process could be used to give a bondable inner layer which was then attached to a conventional FR4 dielectric and an outer top copper layer. The capacitor dielectric had three components comprising barium titanate, a zinc based dopant and a glass that bound them together. Dielectric constants of around 3,000 were achievable. A key to making the technology viable was the minimisation of exposure of the ceramic dielectric to the typical acid chemistries used in the conventional PCB fabrication process.

The second paper covered the electrical behaviour of thin film embedded decoupling capacitors in printed circuit boards and was presented by Seok-Kyo Lee who was from Samsung Electromechanics-Company of Suwon, Korea. The presentation began by showing the trends in high speed digital systems and the increasing need to control simultaneous switching noise. This could be achieved using discrete decoupling capacitors. By adding more bypass capacitors it was possible to reduce power to ground noise, but this was costly and consumed valuable space. A variety of epoxy based embedded capacitance materials had been used in the study reported and they were compared in terms of their properties. These had dielectric constants varying from around 3.9 up to 30.0 and thicknesses ranging from 12 to 50 μm. Their capacitance values varied from 0.5 to 12.0 nF/in². Using these materials, it had been possible to get a significant improvement in power to ground impedance and consequent suppression of simultaneous switching noise. The study had demonstrated that thin film embedded capacitors gave a better high frequency performance than with discrete decoupling capacitors. Further work was being carried out with a 14 layer board that contained two high capacitance layers and very thin power/ground cores. Reliability testing had also been carried out including solder shock, highly accelerated stress testing and temperature humidity bias and there were no issues.

The final paper of this session was on “Dielectric Materials for Embedded Capacitors in PWBs” and was given by Kazunori Yamamoto of Hitachi Chemical Company Limited Shimodate, Ibaraki, Japan. The presentation began with an overview of embedded passive technologies, the routes by which they could be made and the materials used. A new embeddable resin-coated copper foil was then described which had been developed for use in capacitor formation. The material was composed of a thermosetting resin and a high dielectric constant filler. In order to obtain high capacitance values, high filler loadings were needed along with a thin dielectric layer. Consequently, the material employed a multimodal particle size distribution to enable a high filler loading and dielectric constants of 45 at 1 MHz had been achieved with excellent stability and good reliability. (Work had been carried out to reduce the incidence of CAF type failures by the use of a special surfactant.) The manufacturing process for using this material was described. Capacitance densities of 20 pF/mm² could be achieved and the noise suppression capability was 10 times higher than for materials derived from conventional FR4. The next target would be for a material with a dielectric constant of >60 and capacitance densities of >1,000 pF/mm².

The keynote speaker on Thursday morning was Jim McElroy of the International Electronics Manufacturing Initiative (INEMI) and he gave an overview of the 2004 INEMI Technology Roadmap. INEMI had over 70 member organisations representing a broad spectrum of the electronics industry supply chain. During preparation of the roadmap INEMI had maintained strong links with other industry roadmaps and the intention was to develop a situational analysis and increased strategic vision for the 10 years from 2005 to 2015. The roadmap had been prepared by 470 participating companies, involved 19 working groups and had around 1,200 pages. Some of the major shifts that had been identified were discussed and these included the growth in the cell phone market, the blurring between computers and communications, the emergence of wireless, digital camera growth, added electronic functionality in automotive applications and the 12 per cent p.a. growth of system in a package (SIP). SIP production was predicted to be 3.25 billion units by 2008. Another key technology challenge that would happen by 2015 was the predicted end of semiconductor scaling, i.e. Moore's Law would no longer apply, and there was a need to start to develop alternative technology as soon as possible. Other important changes were the slow down in the growth of chip size, the encroachment of LCD and plasma technologies on conventional CRT displays, the evolution of new storage technologies and the impact of global environmental legislation. It was stated that substrate, component and IC package costs should drop by 30 per cent in the next 5 years and by 60 per cent over the next 10 years. Some of the other key growth areas were outlined and these included high speed internet and voice over internet (VOIP). Additional significant changes highlighted included the need to develop sustainable processes, the potential impact of the REACH legislation and the continuing move of assembly to China. Integrated passive components would be needed to achieve forthcoming wiring density and electrical performance targets. Emerging device requirements were driving the need for new packaging technologies. There was also a strong need for improved design tools for both buried component and opto wiring boards and test procedures for electro/ optical systems were required. Another interesting observation was that the materials supply base often did not have adequate demand (at high enough margins) to drive many of the new materials developments. A key recommendation from the roadmap was that there was a need from an interconnect perspective to explore dimensional stability of PWB materials because of the increasingly stringent demands for fine pitch and microvia use. An explanation was also given of how the IPC Roadmap focused purely on interconnect technology and fed into the INEMI Roadmap. Key interconnect developments mentioned were the continuing increase in board layer count and the growing use of mixed laminate material structures.

The first technical session of the day was on Surface Finishes and was chaired by Nancy Jaster of Lucent Technologies Inc. The first of two papers was presented by George Milad (Plate 3) from the Uyemura International Corporation Technical Centre in Southington, Connecticut, USA and his paper was entitled “Direct Immersion Gold (DIG) as a Final Finish”. The DIG finish was a directly applied deposit of gold onto copper using a catalytic rather than immersion process, i.e. no nickel layer was used as in more conventional ENIG systems. Typical film thicknesses of 30-80 μm were used, but higher thicknesses could be applied if a wire bonding capability was required. Twenty minutes of plating would typically give a 50 nm thickness of gold but the plating rate was linear with time unlike with a conventional immersion process. The influence of original copper surface topography on solderability had been investigated and a special etching agent was developed to give optimum copper surface roughening. It was found that a rougher surface gave better solder spreading and that spreading with lead-free alloys was inferior to that of conventional tin-lead solder. Solder ball shear testing was also carried out and the impact of high temperature storage was evaluated by using storage at 150°C for up to 1,000 h. The formation of intermetallics was studied during this high temperature storage with both SAC and tin-lead solder alloys. For gold wire bonding a thicker gold deposit would be needed and this required an additional electroless plating step to be added. For good wire bonding a gold thickness of 500 nm was required. Good wire bond pull strengths had been obtained with only 50 nm of gold, but these deteriorated significantly after thermal storage. With the 500 nm gold thickness, thermal storage had virtually no deleterious effect on the wire bond pull strength.

Plate 3 George Milad

The second paper was given by Donald Cullen of MacDermid Inc, Waterbury, Connecticut and his presentation was on the “Characterisation, reproduction and resolution of solder joint microvoiding”. Microvoids were defined and compared to other types of voids and their impact on ball shear strength was shown. Microvoiding could also have a subtle effect on the quality of the solder joints and there was a need to adopt better PCB manufacturing process control as this could influence the formation of microvoid formation. Void size limitations were defined in the IPC standard 7095. Work had been carried out to assess the influence of a silver surface finish process on the incidence of microvoiding. Factors such as bath age, silver thickness and etch type were evaluated. A high thickness of silver on the solder pads was found to increase the occurrence of microvoiding and a slightly reduced silver thickness of 0.15-0.45 μm was now recommended. Many other possible factors that could lead to microvoiding were also detailed.

Session S32 was on Pulse Plating Technology and the session leader was Dave McGregor of DuPont. The first paper was given by Stefan Gerhold of Atotech Deutschland, Berlin, Germany and his paper was entitled “Site-specific measurement of cathodic pulse shape and plating current density for optimisation of pulse plating lines”. Stefan introduced the reasons why pulse plating had been adopted in recent years and these included the high throwing power that could be achieved. Pulse wave forms could be checked using an oscilloscope, but this only provided a snapshot, gave no information about local deviations and it was not site specific enough. A better method was known as Optipulse and was a site specific in situ measurement of cathodic plating current density. The method required a special test board with five, seven or nine etched islands on the surface. With the combination of the island method and the use of high data sample frequencies, an 80 channel system was able to measure the cathodic plating current density in situ, site specifically and time resolved. The method was not limited to PCB production and it enabled the influence of pulse shapes on crystal structure and throwing power etc., to be studied.

The next paper was given by Roger Mouton on behalf of Dr Gert Nelissen of Vrije Universiteit Brussels (VUB) in Belgium and was entitled “A Performance Simulation Tool for Bipolar Pulsed PCB Plating”. The presentation described work that had been carried out on plating simulation to improve product quality and processing speeds. The process modelling strategy involved the use of 3D modelling software to address plating at the macro, meso and micro levels and this involved a range of factors from those as large as tank design through to PCB design and down to fluid dynamics on vias. The focus was on the mesoscale current density distribution problems (i.e. non- uniform layer thickness distribution caused by the circuit board layout). Data were shown from the results of the incorporation of pulse plating parameters with the computer modelling. The use of 3D modelling for PCB plating optimisation gave a highly reliable prediction of current and layer thickness distributions at the macro and meso level including PCB layout. It also gave highly reliable predictions of current and layer thickness distributions at the micro level, i.e. for blind vias and through holes. The use of this approach was claimed to enable savings in soldermask, copper metal and dry film costs.

One of the final technical sessions of the convention was on Plating Optimisation (Plate 4) and this was chaired by Dr Martin Goosey of Rohm and Haas Electronic Materials in Coventry, England. The first paper of the session was given by Hideki Hagiwara of the Kanto Gakuin University in Japan and his presentation was entitled “Characterisation of acid copper plating solutions for via filling”. The work reported in this presentation was of the study of the mechanical properties of copper films plated using two types of conformal acid copper plating baths that had been in use for some time and two types of acid copper plating baths designed for via filling. Throwing power and thermal resistance were evaluated by thermally shocking boards at 260°C for 5s in silicone oil. Other properties evaluated included stress and hardness measurements, as well as elongation and tensile stress. From this work the selection of suitable additives was confirmed as being of great importance in determining the performance of copper plating baths for via filling. It was reported that a drop in the mechanical properties of plated films due to co-deposition of the additives was difficult to overcome even by annealing and thus the selection of the best additives was essential for obtaining films with desirable mechanical properties.

Plate 4 Speakers and Chair of the Plating Optimisation Sessions

The second paper was from Charles “Chuck” Schutz of Serfilco Ltd, Northbrook, Illinois and his presentation focused on “Improving printed circuit board plating with eductor agitation”. Chuck began by stating that eductors were first used in the plating industry in the early 1990s to replace air agitation. Agitation was used to produce a bright deposit, to prevent burning in high current density areas and to prevent pitting. Air agitation had a number of deficiencies such as the creation of foam and chemical mists, it also increased oxidation, accelerated heat loss to air and increased additive air usage. The method of operation of eductors was described and they were said to make use of the venturi principle in order to convert high pressure flow to low pressure, high volume flow. Case histories were given that showed the benefits of using eductor agitation. These included reduced brightener usage, faster plating via use of higher plating current densities, heat savings and increased productivity.

The final paper of the session was given by Joseph D'Ambrisi of MacDermid and was called “Bridging the Gap – Technical Capabilities of a Direct Plate PTH process”. The paper focused on the use of carbon based direct plate systems and it was stated that currently only 15 per cent of boards were processed using a direct plate process. However, over 60 per cent of PC mother boards were currently made with a carbon based direct plate process. Also, a wide range of board types could be processed with this approach and the process had only four discrete chemical stages compared with seven for an electroless copper process. This offered the potential for considerable savings and control of the process was much simpler: there was no selective depletion of components and no non-productive side reactions. Jo also referred to the EPA “Design for the Environment” study that was carried out in the mid-1990s to assess the environmental impact of both electroless coppers and various direct plate processes. Data were shown to demonstrate that carbon based direct plate processes could give equivalent or superior performance to electroless copper, even with complex and difficult board designs.

At the end of the formal technical sessions, there was an ECWC closing ceremony at which the main speaker was Burt Rutan of Scaled Composites. Burt gave a fascinating review of the history of manned flight which culminated with remarkable film of his own company's record breaking space flight. It was on 4 October 2004 that SpaceShipOne rocketed into history, becoming the first private manned spacecraft to exceed an altitude of 328,000 feet twice within the span of a 14 day period, thus claiming the 10 million dollar Ansari X Prize. Burt urged renewed interest in manned space flight and his mission was to make it much more accessible, rather than just being restricted to a mere few. Here was a true American pioneer.

In summary, the depth and breadth of the presentations given during the ECWC 10 was remarkable and there was something to satisfy all interests, however, specialized they may have been. As stated at the beginning of this review, it has only been possible to give an overview of just some of the papers that were presented. The more inquisitive reader is therefore recommended to get in touch with individual presenters for more details of their specific presentations or to contact the IPC for a copy of the convention proceedings. The IPC is to be congratulated for organising such and excellent convention. The whole event was extremely well organised and well run. It was a pleasure to attend.

Martin Goosey