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A novel technology for a multichip module (MCM) on silicon is presented. The technology features the integration of a power and a ground plane, resulting in a five‐conductor layer module, the use of the heavily (n⁺) doped Si as the ground plane for integrated decoupling capacitances, integrated low TCR NiCr resistors, low resistance (13mΩ per square) TiW/Cu/TiW metallisation, high quality PECVD oxynitride (SiON) insulation layers, which are optimised to a low stress content, and a new wet‐dry etch technique for the vias. The module is able to handle 200MHz clock frequencies and, when carefully designed, can also be used for opto‐electronic interconnections in the GHz range. A test module for DC and HF characterisation has been designed and produced. Preliminary test results are presented.

The Intelligent MCM Analyser (IMCMA) is a software tool which allows the designer to concurrently assess the reliability of an MCM design based on operational parameters. Traditionally, this type of assessment takes days to accomplish and is performed after the design phase. The Intelligent MCM Analyser does not require the designer to be a thermal/reliability expert and gives an assessment in minutes depending on the complexity of the design and the speed of the computer. IMCMA assists and designer in achieving a robust design which will improve both quality and reliability. The software uses object‐oriented data representation, a blackboard architecture and heuristic expertise to perform lower level reasoning associated with finite element thermal analysis techniques that are normally very tedious and labour intensive. A test case is presented comparing results from IMCMA with the results from a general purpose finite element code. The ultimate pay‐off will be the manufacturer's ability to build higher quality, higher reliability MCMs at a lower cost.

The paper describes a new electro‐optical board technology, based on the discrete wiring principle. Isolated copper wires are embedded in the circuit board to realise the electrical interconnections. Glass optical fibres are embedded to obtain optical interconnections. The technology allows for crossovers and for electrical and optical interconnections on one layer of interconnection. As the technology can be applied on the level of package or multichip module, circuit board and backpanel, it has the ability to offer a complete solution for chip to chip electrical and optical interconnections. The paper will describe the basic manufacturing technology of the boards. The benefits of the technology from a system designer's viewpoint will be addressed. The problem of coupling light in and out of the embedded optical fibres will be discussed and the realisation of a first on‐board optical link via embedded optical fibres will be described.

CMOS devices are approaching the 50 MHz threshold at which conventional electronic assemblies—based on packaged components (SMD, PGA, etc.) mounted on high‐density printed circuit boards—impose a serious penalty on the speed of the raw die provided by the semiconductor vendors. To improve the packaging density and to reduce the resistive and capacitive loads as well as signal delays at the second level of interconnection, new packaging concepts for VLSI and ULSI components are imperative. Multichip modules (MCM) seem to be the only adequate solution to the interconnect problem. Ultrastrate—the author's company's MCM technology with multilayer thin‐film build‐ups—is briefly presented. Life cycles for products in the electronics industry are becoming ever shorter. Electronics engineers must package more complicated circuits in smaller volumes and in a shorter time. On the other hand, prototyping an MCM from the electrical schematic takes at least 12 weeks. There is as yet no equivalent of a PCB breadboard for MCMs! In response to this situation, Polystrate is a new process which has been developed to provide a flexible and fast prototyping tool for MCMs. It satisfies the most stringent requirements with regard to performance, economics and ease of modification, and offers a very fast turn‐around time. The technological synergies between Ultrastrate and Polystrate allow for a smooth transition between the prototyping and production phases.

Existing IC packaging and interconnection is creating a barrier for advances taking place in IC technology. Wafer scale integration (WSI) is being proposed as the next major step in electronics, bringing with it the removal of a large number of these barriers. However, there are still major problems with WSI technology that are unlikely to be solved before the late nineties. In the meantime a new packaging and interconnection technology will be introduced—the multichip module (MCM), which will act as a hybrid for WSI. The MCM will not make the PCB obsolete, though it will pose threats and opportunities to important parts of the thick film hybrid industry. The MCM, for the purposes of this paper, is defined as a thin film multilayer interconnect structure utilising IC manufacturing type processes. MCM technology is not confined to high performance systems; it will be used across the whole of the electronics industry including the consumer sector, with a circuitised substrate world market of nearly $7 bn by 1997.

The paper aims to focus on the semiconductor temperature prediction in the multichip modules by using a simplified 1D model, easy to implement in the electronic simulation tools.

Accurate prediction of temperature variation of power semiconductor devices in power electronic circuits is important for obtaining optimum designs and estimating reliability levels. Temperature estimation of power electronic devices has generally been performed using transient thermal equivalent circuits. This paper has studied the thermal behaviour of the power modules. The study leads to correcting the junction temperature values estimated from the transient thermal impedance of each component operating alone. The corrections depend on multidimensional thermal phenomena in the structure.

The classic analysis of thermal phenomena in the multichip structures, independently of powers’ dissipated magnitude and boundary conditions, is not correct. An advanced 1D thermal model based on the finite element method is proposed. It takes into account the effect of the heat‐spreading angle of the different devices in the module.

The paper focuses on mathematical model of the thermal behaviour in the power module. The study leads to a correction of the junction temperature values estimated from the transient thermal impedance of each component given by manufacturers. The proposed model gives a good trade‐off between accuracy, efficiency and simulation cost.

A high‐density module for image processing was developed by chip‐on‐wafer technology. A silicon wafer was used as the substrate and the LSI chips were flip‐chip bonded to the silicon wafer by bumps in chip‐on‐wafer technology. A primary benefit of using a silicon wafer is the little induced thermal stress which affects the bumps. The module contained a digital signal processor, SRAMs and other peripheral LSls. A total of sixteen chips were bonded on the wafer. The LSIs were connected to each other by copper/polyimide multilayer interconnections consisting of eight copper conductive layers and polyimide dielectric layers. The characteristic impedance for the signal lines was controlled to 50 ohms. The LSIs were connected to the wafer electrically and mechanically by solder bumps, which were formed on the LSI bonding pads. A 188 pin AIN ceramic package was used for the module in order to obtain high heat radiation and high reliability. The occupied area for the module was reduced to 20%, compared with the size for conventionally assembled DIPs on a PC board.

An innovative embedded chip MCM technology is being developed to address the packaging needs of the high volume, non‐military electronics industries. This development has evolved out of the GE High Density Interconnect (HDI) embedded chip MCM technology that was aimed at very high performance electronics in harsh military environments. In the HDI process, multiple bare chips are placed into cavities formed in a ceramic substrate and interconnected using an overlay polymer film, thin film metallisation and laser formed vias. Multiple levels of fine line (20 to 40 microns) interconnections and reference planes are used to form the circuit. In this new process, a plastic encapsulated substrate is formed by moulding a polymer resin around the bare die after placement on to a flat polymer film pre‐coated with an adhesive layer. After curing of the resin, the circuit is formed by patterning via holes through the polymer film to the components, metallising the polymer film and patterning the metal into the desired interconnect pattern. Feature sizes are readily scaled to the complexity needed by the circuit, permitting the use of lower cost and higher yield board photopatterning processes and equipment. This paper will cover the development of this low cost technology and will describe the process. It will also describe the thermal, mechanical and electrical features of this process and show actual working prototype modules.

ISHM invites papers for the above Conference, to be held on 29–31 May 1991 in Rotterdam, The Netherlands. Papers should cover areas such as: design, manufacturing, packaging and interconnection, materials and processing, applications, reliability, components, new technologies, marketing and economics, optoelectronics. Summaries should be in English, length 200–300 words. The deadline for receipt of summaries is 30 September 1990. (For full details, see announcement on pp. 54–55.)

Diffusion patterning is a dielectric patterning technology, which is used in the screen printed thick film technology for higher density multilayer circuits. This technology is suitable for producing lower cost multichip modules and requires a low additional investment in conventional thick film technology production lines. Comparisons of via resolution capability of diffusion patterning versus conventional thick film technology are described and discussed. Preliminary experimental results obtained with a test circuit showed that 200μm lines and 200μm vias could be achieved with acceptable yield and with minimal modification to standard production lines. The electronic circuit for the pressure sensor was designed and realised with the verified technology as a low‐cost ceramic multichip module. A few results of an investigation of some thick film materials, which comprise the “set” of pastes for diffusion patterning technology, are presented.