Search results

The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications.

The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

This paper aims to present a design and simulation of electrostatic nanoelectromechanical system (NEMS)-based logic gates using laterally actuated cantilever with double-electrode structure that can implement logic functions, similar to logic devices that are made of solid-state transistors which operates at 5 V.

The analytical modeling of NEMS switch is carried out for finding the pull-in and pull-out voltage based on Euler-Bernoulli’s beam theory, and its numerical simulation is performed using finite element method computer-aided design tool COVENTORWARE.

This paper reports analytical and numerical simulation of basic NEMS switch to realize the logic gates. The proposed logic gate operates on 5 V which suits well with conventional complementary metal oxide semiconductor (CMOS) logic which in turn reduces the power consumption of the device.

The proposed logic gates use a single bit NEMS switch per logic instead of using 6-14 individual transistors as in CMOS. One exclusive feature of this proposed logic gates is that the basic NEMS switch is structurally modified to function as specific logic gates depending upon the given inputs.

Although scholars increasingly use institutional logics to explain macro-level phenomena, we still know little about the micro-level psychological mechanisms by which institutional logics shape individual action. In this paper, we propose that individuals internalize institutional logics as an associative network of schemas that shapes individual actions through a process we call institutional frame switching. Specifically, we conduct two novel experiments that demonstrate how one particularly important schema associated with institutional logics – the implicit theory – can drive individual action. This work further develops the psychological underpinnings of the institutional logics perspective by connecting macro-level cultural understandings with micro-level situational behavior.

The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and the corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding m-ary (many-valued) extensions for the use in nano systolic networks are introduced. The first part of the paper presents important fundamentals with regards to systolic computing and carbon-based field emission that will be utilized in the implementations within the second part of the paper.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power very-large-scale-integration circuit design for signal processing applications.

The purpose of this paper is to introduce an approach for m‐valued classical and non‐classical (reversible and quantum) optical computing. The developed approach utilizes new multiplexer‐based optical devices and circuits within switch logic to perform the required optical computing. The implementation of the new optical devices and circuits in the optical regular logic synthesis using new lattice and systolic architectures is introduced, and the extensions to quantum optical computing are also presented.

The new linear optical circuits and systems utilize coherent light beams to perform the functionality of the basic logic multiplexer. The 2‐to‐1 multiplexer is a basic building block in switch logic, where in switch logic a logic circuit is implemented as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less‐costly in synthesizing wide variety of logic circuits and systems. The extensions to quantum optical computing using photon spins and the collision of Manakov solitons are also presented.

New circuits for the optical realizations of m‐valued classical and reversible logic functions are introduced. Optical computing extensions to linear quantum computing using photon spins and nonlinear quantum computing using Manakov solitons are also presented. Three new multiplexer‐based linear optical devices are introduced that utilize the properties of frequency, polarization and incident angle that are associated with any light‐matter interaction. The hierarchical implementation of the new optical primitives is used to synthesize regular optical reversible circuits such as the m‐valued regular optical reversible lattice and systolic circuits. The concept of parallel optical processing of an array of input laser beams using the new multiplexer‐based optical devices is also introduced. The design of regular quantum optical systems using regular quantum lattice and systolic circuits is introduced. New graph‐based quantum optical representations using various types of quantum decision trees are also presented to efficiently represent quantum optical circuits and systems.

The introduced methods for classical and non‐classical (reversible and quantum) optical regular circuits and systems are new and interesting for the design of several future technologies that require optimal design specifications such as super‐high speed, minimum power consumption and minimum size such as in quantum computing and nanotechnology.

The purpose of this paper is to introduce new non‐classical implementations of neural networks (NNs). The developed implementations are performed in the quantum, nano, and optical domains to perform the required neural computing. The various implementations of the new NNs utilizing the introduced architectures are presented, and their extensions for the utilization in the non‐classical neural‐systolic networks are also introduced.

The introduced neural circuits utilize recent findings in the quantum, nano, and optical fields to implement the functionality of the basic NN. This includes the techniques of many‐valued quantum computing (MVQC), carbon nanotubes (CNT), and linear optics. The extensions of implementations to non‐classical neural‐systolic networks using the introduced neural‐systolic architectures are also presented.

Novel NN implementations are introduced in this paper. NN implementation using the general scheme of MVQC is presented. The proposed method uses the many‐valued quantum orthonormal computational basis states to implement such computations. Physical implementation of quantum computing (QC) is performed by controlling the potential to yield specific wavefunction as a result of solving the Schrödinger equation that governs the dynamics in the quantum domain. The CNT‐based implementation of logic NNs is also introduced. New implementations of logic NNs are also introduced that utilize new linear optical circuits which use coherent light beams to perform the functionality of the basic logic multiplexer by utilizing the properties of frequency, polarization, and incident angle. The implementations of non‐classical neural‐systolic networks using the introduced quantum, nano, and optical neural architectures are also presented.

The introduced NN implementations form new important directions in the NN realizations using the newly emerging technologies. Since the new quantum and optical implementations have the advantages of very high‐speed and low‐power consumption, and the nano implementation exists in very compact space where CNT‐based field effect transistor switches reliably using much less power than a silicon‐based device, the introduced implementations for non‐classical neural computation are new and interesting for the design in future technologies that require the optimal design specifications of super‐high speed, minimum power consumption, and minimum size, such as in low‐power control of autonomous robots, adiabatic low‐power very‐large‐scale integration circuit design for signal processing applications, QC, and nanotechnology.

Scholarly research has increasingly emphasised the need for more research that provides fine-grained empirical accounts of how context plays a role in sensemaking. The purpose of this paper is to provide an in-depth look at how broader institutional context shapes the sensemaking of organisational change in a novel empirical context of a Pakistani commercial bank.

A qualitative inductive case study of a commercial bank using interviews and archival material.

Actors make sense of an organisational change initiative by accessing broader societal institutional logics when the field-level organisational logics are not plausible. The consequences of such frame switching may include the provocation of emotionally charged perceptions of politics and moral valuations of legitimacy.

This study is based on a single organisational case study in a particular national context.

This study urges organisational change leaders to consider the role of informal interpersonal relationships and culturally shaped, and emotionally charged, perceptions of change among the change recipients, beyond the technical considerations of the industry concerned. Instead of just focussing on official interaction and top-down communication, along with creating top-level “guiding coalitions” to manage change, organisational leaders need to be sensitive to informal channels at the lower rungs of the organisation to pick emotional reactions of change recipients.

The study contributes to the literature on sensemaking of organisational change by showing how the institutional context, a neglected factor in the literature, impacts sensemaking. The study also contributes to the empirical literature on microfinance (MF) by providing an in-depth account of a commercial bank that introduced MF as a product line.

‘Fluidics has become a bit of a dirty word among a lot of engineers; I try to avoid using it.’ The words don't sound like those of an engineer confident in his chosen field, but they reflect a feeling that's pretty widespread in the world of fluidics—or, to use the term this par‐ticular engineer would prefer, fluid logic.

The present work aims to explain how the nonlinear average model can be used in power electronic integration design as a behavioral model.

The nonlinear average model is used in power electronic integration design as a behavioral model, where it is applied to a voltage source inverter based on IGBTs. This model was chosen because it takes into account the nonlinearity of the power semiconductor components and the wiring circuit effects, which can be formalized by the virtual delay concept. In addition, the nonlinear average model cannot distinguish between slow and quick variables and this is an important feature of the model convergence.

The paper studies extensively the construction of the nonlinear average model algorithm theoretically. Detailed explanations of the application of this model to voltage source inverter design are provided. The study demonstrates how this model illustrates the effect of the nonlinearity of the power semiconductor components' characteristics on dynamic electrical quantities. It also predicts the effects due to wiring in the inverter circuit.

More simulations and experimental analysis are still necessary to improve the model's accuracy, by using other static characteristic approaches, and to validate the applicability of the model to different converter topologies.

The paper formulates a simple nonlinear average model algorithm, discussing each step. This model was described by VHDL‐AMS. On the one hand, it will assist theoretical and practical research on different topologies of power electronic converters, particularly in power integration systems design such as the integrated power electronics modules (IPEM). On the other hand, it will give designers a more precise behavioral model with a simpler design process.

The nonlinear average model used in power electronic integration design as behavioral model is a novel approach. This model reduces computational costs significantly, takes physical effects into account and is easy to implement.

This study aims to propose a unique algorithm-based hysteresis current control technique (HCCT) for induction motor using a single-phase voltage source inverter (SPVSI) to eliminate both sub and inter harmonics (SIH) and electromagnetic interference (EMI). The total harmonic distortion (THD) of the load current also reduces in comparison to standard HCCT and modified technique-based existing HCCT.

Matlab simulation has been carried out to develop an SPVSI model and the unique algorithm-based HCCT. The same platform has also been used to develop a few existing HCCTs such as standard, dual-band and modified. The switching frequency and harmonic analysis of load currents for all the HCCTs have been compared in the paper. The hardware implementation of the proposed algorithm-based HCCT was also verified and compared with the simulation results.

The proposed unique algorithm-based HCCT provides the benefits of both unipolar and bipolar switching techniques. It reduces the switching frequency as unipolar switching scheme and eliminates the EMI. It also reduces THD and nullifies SIH of the load current. This enables an improvement in the overall performance and efficiency of the motor.

This proposed HCCT eliminates the SIH and improves the overall efficiency of the motor, hence can prevent overheating, vibration, acoustic noise, pulsating torque and braking of the rotor shaft of the motor and increasing the reliability of the system.

It can be implemented for the motors that are used in household applications and electric vehicles through one-phase inverter.

This proposed HCCT has detected the zero crossing point of reference current, allowed samples and shifted the necessary amount of hysteresis band at zero crossing region to eliminate SIH and THD.