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This paper aims to investigate the influence of composite solder joint preparation on the thermal properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the mechanical strength of the soldered joint.

Reinforced composite solder joints with the addition of titanium oxide nanopowder (TiO₂) were prepared. The reference alloy was Sn99Ag0.3Cu0.7. Reinforced joints differed in the weight percentage of TiO₂, ranging from 0.125 to 1.0 Wt.%. Two types of components were used for the tests. The resistor in the 0805 package was used for mechanical strength tests, where the component was soldered to the FR4 substrate. For thermal parameters measurements, a power element MOSFET in a TO-263 package was used, which was soldered to a metal core printed circuit board (PCB) substrate. Components were soldered in batch IR oven.

Shear tests showed that the addition of titanium oxide does not significantly increase the resistance of the solder joint to mechanical damage. Titanium oxide addition was shown to not considerably influence the soldered joint’s mechanical strength compared to reference samples when soldered in batch ovens. Thermal resistance R_thj-a of MOSFETs depends on TiO₂ concentration in the composite solder joint reaching the minimum R_thj at 0.25 Wt.% of TiO₂.

Mechanical strength: TiO₂ reinforcement shows minimal impact on mechanical strength, suggesting altered liquidus temperature and microstructure, requiring further investigation. Thermal performance: thermal parameters vary with TiO₂ concentration, with optimal performance at 0.25 Wt.%. Experimental validation is crucial for practical application. Experimental confirmation: validation of optimal concentrations is essential for accurate assessment and real-world application. Soldering method influence: batch oven soldering may affect mechanical strength, necessitating exploration of alternative methods. Thermal vs mechanical enhancement: while TiO₂ does not notably enhance mechanical strength, it improves thermal properties, highlighting the need for balanced design in power semiconductor assembly.

Incorporating TiO₂ enhances thermal properties in power semiconductor assembly. Optimal concentration balancing thermal performance and mechanical strength must be determined experimentally. Batch oven soldering may influence mechanical strength, requiring evaluation of alternative techniques. TiO₂ composite solder joints offer promise in power electronics for efficient heat dissipation. Microstructural analysis can optimize solder joint design and performance. Rigorous quality control during soldering ensures consistent thermal performance and mitigates negative effects on mechanical strength.

The integration of TiO₂ reinforcement in solder joints impacts thermal properties crucial for power semiconductor assembly. However, its influence on mechanical strength is limited, potentially affecting product reliability. Understanding these effects necessitates collaborative efforts between researchers and industry stakeholders to develop robust soldering techniques. Ensuring optimal TiO₂ concentration through experimental validation is essential to maintain product integrity and safety standards. Additionally, dissemination of research findings and best practices can empower manufacturers to make informed decisions, fostering innovation and sustainability in electronic manufacturing processes. Ultimately, addressing these social implications promotes technological advancement while prioritizing consumer trust and product quality in the electronics industry.

The research shows the importance of the soldering technology used to assemble MOSFET devices.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

This study aims to regarding the application of traditional pulse frequency modulation control full-bridge LLC resonant converters in wide output voltage fields such as on-board chargers, there are issues with wide frequency adjustment ranges and low conversion efficiency.

To address these issues, this paper proposes a fixed-frequency pulse width modulation (PWM) control strategy for a full-bridge LLC resonant converter, which adjusts the gain by adjusting the duty cycle of the switches. In the full-bridge LLC converter, the two switches of the lower bridge arm are controlled by a fixed-frequency and fixed duty cycle, with their switching frequency equal to the resonant frequency, whereas the two switches of the upper bridge arm are controlled by a fixed-frequency PWM to adjust the output voltage. The operation modes of the converter are analyzed in detail, and a mathematical model of the converter is established. The gain characteristics of the converter under the fixed-frequency PWM control strategy are deeply analyzed, and the conditions for implementing zero-voltage switching (ZVS) soft switching in the converter are also analyzed in detail. The use of fixed-frequency PWM control simplifies the design of resonant parameters, and the fixed-frequency control is conducive to the design of magnetic components.

According to the fixed-frequency PWM control strategy proposed in this paper, the correctness of the control strategy is verified through simulation and the development and testing of a 500-W experimental prototype. Test results show that the primary side switches of the converter achieve ZVS and the secondary side rectifier diodes achieve zero-current switching, effectively reducing the switching losses of the converter. In addition, the control strategy reduces the reactive circulating current of the converter, and the peak efficiency of the experimental prototype can reach 95.2%.

The feasibility of the fixed-frequency PWM control strategy was verified through experiments, which has significant implications for improving the efficiency of the converter and simplifying the design of resonant parameters and magnetic components in wide output voltage fields such as on-board chargers.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

This study aims to solve the problem that both the speed and the required driving power of electric vehicles (EVs) will change during the dynamic wireless charging (DWC) process, making it difficult to charge EVs with a constant power considering the overall efficiency of DWC system, the numbers of EVs and the power supply capacity. Therefore, this paper proposes the power control and efficiency optimization strategies for multiple EVs.

The wireless power charging system for multiple loads with a structure of double-sided LCC compensation topology is established. The expressions of optimal transmission efficiency and optimal equivalent impedance are derived. Taking the Tesla Model 3 as an example, a method to determine the number of EVs allowed by one transmitter coil and the overall charging power is proposed considering EV speed, power supply capacity, safe braking distance and overall efficiency. Then, the power control strategy, which can adapt to the changes of EV speed and the efficiency optimization strategy under different numbers of EVs are proposed.

In this paper, a method to determine the numbers of EVs allowed by one transmitter coil and the overall charging power is proposed considering EVs speed, power supply capacity, safe braking distance and overall efficiency. The accuracy of the charging power is good enough and the overall efficiency reaches a maximum of 91.79% when the load resistance changes from 5Ω to 20Ω.

In this paper, the power control and efficiency optimization strategy of DWC system for multiple EVs are proposed. Specifically, a method of designing the number of EVs and charging power allowed by one transmitter coil considering the factors of EV speed, power supply capacity, safe braking distance and overall efficiency is designed. The overall efficiency of the experiment reaches a maximum of 91.79% after adopting the optimization strategy.

High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.

Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.

Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.

The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.