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The purpose of this paper is to provide a systematic review on technical findings and discuss the feasibility and future of gold (Au) wirebonding in microelectronics packaging. It also aims to study and compare the cost, quality and wear-out reliability performance of Au wirebonding with respect to other wire alloys such as copper (Cu) and silver (Ag) wirebonding. This paper discusses the influence of wire type on the long-term reliability tests.

Literature reviews are conducted based on cost and wire selections of Au, Cu or Ag wirebonding. Detailed wear-out failure findings and wire selection with cost considerations are presented in this review paper. The future and the status of Au wirebonding in microelectronics packaging are discussed in this paper.

This paper briefly reviews selected aspects of the Au ball and other alternative bonding options, focusing on reliability performance, and discusses the future of Au wirebonding in the near future in semiconductor packaging.

The paper reveals the technical considerations when choosing the wire types for future microelectronics packaging.

The in-depth technical review and strategies of the selection of wire types (Au, Cu or the latest Ag alloy) in microelectronics packaging are discussed in this paper based on previous literature studies.

The purpose of this paper is to provide a systematic method to perform long‐term reliability assessment of gold (Au) and copper (Cu) ball bonds in fineline ball grid array package. Also with the aim to study the apparent activation energies (E_aa) and its associated wearout mechanisms of both Au and Cu wire in semiconductor device packaging. This paper discusses the influence of wire type on the long‐term reliability and mechanical performance after several component reliability stress tests.

A fineline ball grid array (FBGA) package with Cu and Au wire bonds was assembled with green molding compound and substrate. Samples are subjected for long‐term high temperature storage bake test at elevated temperatures of 150°C, 175°C and 200°C. Long‐term reliability plots (lognormal plots) are established and E_aa of both ball bonds are determined from Arrhenius plots. Detailed failure analysis has been conducted on failed sample and HTSL failure mechanisms have been proposed.

Reliability results show Au ball bond in FBGA package is observed with higher hour‐to‐failure compared to Cu ball bonds. The E_aa value of high temperature storage life (HTSL) reliability for Au ball bond is lower than Cu ball bond. Typical HTSL failure mechanism of Au ball bond is induced by micro‐voiding and AuAl intermetallic compound (IMC) micro‐cracks while CuAl IMC micro‐cracking (induced by Cl⁻ corrosion attack and micro‐cracking) caused wearout opens in Cu ball bond. These test results affirm the test‐to‐failure data collected is a useful method for lifetime prediction and E_aa calculation.

The paper reveals higher reliability performance of Cu ball bond in FBGA flash memory package which can be deployed in flash memory FBGA packaging with optimised package bill of materials.

The test‐to‐failure methodology is a useful technique for wearout reliability prediction and E_aa calculation.

This paper aims to investigate the root causes of and implement the improvements for the inter layer dielectric (ILD) crack for LQFP C90FG (CMOS90 Floating Gate) wafer technology devices in copper wire bonding process.

Failure analysis was conducted including cratering, scanning electron microscopy inspection and focus ion beam cross-section analysis, which showed ILD crack. Root cause investigation of ILD crack rate sudden jumping was carried out with cause-and-effect analysis, which revealed the root cause is shallower lead frame down-set. ILD crack mechanism deep-dive on ILD crack due to shallower lead frame down-set, which revealed the mechanism is lead frame flag floating on heat insert. Further investigation and energy dispersive X-ray analysis found the Cu particles on heat insert is another factor that can result in lead frame flag floating.

Lead frame flag floating on heat insert caused by shallower lead frame down-set or foreign matter on heat insert is a critical factor of ILD crack that has never been revealed before. Weak wafer structure strength caused by thinner wafer passivation1 thickness and sharp corner at Metal Trench (compared with the benchmarking fab) are other factors that can impact ILD crack.

For ILD crack improvement in copper wire bonding, besides the obvious factors such as wafer structure and wire bonding parameters, also should take other factors into consideration including lead frame flag floating on heat insert and heat insert maintenance.

Knowledge of critical materials and process parameters necessary to fabricate quality copper thick film multilayer and hybrid circuits is being amassed and distributed throughout the industry via technical reports and presentations. Generally the information being provided in a single report deals with specific segments of the industry or only one or two specific nitrogen fireable materials. In order for hybrid manufacturers to commit themselves to the technology they need to know that sufficient flexibility exists to permit design of complex circuits and accommodate circuit design changes without imposing changes in basic process guidelines and controls. The OEM's concern, which is valid, has been that the investment required for capital equipment and establishing new processes must be fully supported by and provide reasonable return from the technology being initiated. This paper introduces new information on wire bonding in copper thick film circuits and some improvements in nitrogen fireable resistor characteristics and processing. Materials are available to produce a broad range of circuits without varying basic process parameters, and adding wirebonding as an interconnect capability further expands the circuit complexity and density achievable with copper thick films.

In this study a multilayer hybrid circuit for high frequency digital systems using Cu conductors was fabricated. The available Cu pastes were evaluated in terms of their applicability and a complex multilayer interconnection circuit was realised and optimised using both the DuPont and Heraeus Cu thick film systems. Also, AI‐1% Si wedge bonding on Cu thick film was investigated. The pull strengths were measured before and after ageing (high temperature storage). Results indicate that Al wire bonding on Cu is technologically feasible and gives no reliability problems.

The driving forces behind recent significant improvements in organic packages for microelectronic applications are electrical performance, product weight, size and manufacturing cost. A very careful selection of optimum manufacturing processes, equipment and materials, and stringent control of critical manufacturing operations are prerequisites for success in this emerging market place. Major technical and business related challenges to a printed circuit board manufacturer who plans to enter this market are discussed.

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

High Q on‐chip inductors and low loss on‐chip interconnects and transmission lines are an important roadblock for the further development of Si‐based technologies at RF and microwave frequencies. In this paper, inductors are realized on standard Si wafers (20 Ω.cm) using MCM‐D processing. This consists of realizing two low K dielectric layers (BCB) and a thick Cu interconnect layer. Inductors with 5 μm lines and spaces are demonstrated for a 5 μm thick Cu layer, hereby leading to a very compact and high performance inductors: Q‐factors in the range of 25 to 30 have been obtained for inductances in the range of 1 to 5 nH. It is also shown how the Q‐factor and resonance frequency vary as a function of the inductor layout parameters and the thickness of the BCB and Cu layers. The realized 50 Ω CPW lines (lateral dimension of 40 μm) have a measured loss of only 0.2 dB/mm at 25 GHz.

An innovative embedded chip MCM technology is being developed to address the packaging needs of the high volume, non‐military electronics industries. This development has evolved out of the GE High Density Interconnect (HDI) embedded chip MCM technology that was aimed at very high performance electronics in harsh military environments. In the HDI process, multiple bare chips are placed into cavities formed in a ceramic substrate and interconnected using an overlay polymer film, thin film metallisation and laser formed vias. Multiple levels of fine line (20 to 40 microns) interconnections and reference planes are used to form the circuit. In this new process, a plastic encapsulated substrate is formed by moulding a polymer resin around the bare die after placement on to a flat polymer film pre‐coated with an adhesive layer. After curing of the resin, the circuit is formed by patterning via holes through the polymer film to the components, metallising the polymer film and patterning the metal into the desired interconnect pattern. Feature sizes are readily scaled to the complexity needed by the circuit, permitting the use of lower cost and higher yield board photopatterning processes and equipment. This paper will cover the development of this low cost technology and will describe the process. It will also describe the thermal, mechanical and electrical features of this process and show actual working prototype modules.

A low cost multichip module employing solder bumped flip chips mounted on an organic substrate was demonstrated. This functional prototype was used to help assess the preliminary feasibility of low temperature solder bumped flip chip applications, from wafer design, sourcing and bumping, substrate design and fabrication, to MCM‐L assembly.