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The paper aims to discuss problems of power and energy losses in a double-circuit overhead transmission line. It was observed from energy meters’ readings, that in such a line, active power losses can be measured as “negative”. The “negative” active power losses appear when the active power injected to the circuit is lower than the active power received at the circuit end. The purpose of this paper is to explain this phenomenon.

Theoretical considerations based on mathematical model of the transmission line of π-type confirming that effect are presented. Power losses related to series impedance of the line and to shunt admittance are calculated. The theoretical considerations are confirmed by measurements done on the real transmission line.

The calculations allow to indicate components of the active power losses, i.e. related to electromagnetic coupling among wires of a given circuit, related to electromagnetic coupling between circuits and related to shunt capacitance asymmetry. The authors indicate the influence of the line/wires geometry on the active power losses in a double-circuit overhead transmission line.

Explanation of the effect of “negative” active power losses’ measurement in a double-circuit overhead transmission line is provided in this paper.

Printed (circuit) boards have been used in the electronics industry for the past 25 years and more. The technology used to design and manufacture PCBs is well known and accepted. Recently, however, designers of electronic equipment have shown that the use of newer materials and systems, such as flexible and moulded circuits, hybrid circuits, or a combination of these, can significantly improve the cost/performance ratio for electronic interconnects. This paper examines some of the many possibilities open to electronics designers and how these new opportunities can improve the economics and performance of electronic equipment.

This paper aims to design a radio frequency micro-electro-mechanical system (RF MEMS)-based phase shifter using chamfered coplanar waveguide (CPW) transmission line (t-line) with open-circuit interdigital metal–air–metal (ID MAM) capacitors.

The proposed phase shifter achieves maximum differential phase shift with low loss at Ku band. The phase shifter is built with one switchable fixed-fixed beam (MEMS switch) on chamfered CPW t-line in series with two planar open-circuit ID MAM capacitors. An equivalent circuit model for the proposed phase shifter is derived, and its parameters are extracted using an electromagnetic (EM) solver.

The MEMS switch is actuated using an electrostatic method with the calculated residual stress of 44.26 MPa. The fabricated phase shifter exhibits low insertion loss, close to 0.14 dB at 17 GHz, with the maximum phase shift of 15.06°. The return loss is greater than 23 dB between 12 and 18 GHz.

This phase shifter presents a promising solution for low loss applications in the Ku band with a maximum phase shift. As the maximum phase shift of 15.06° is achieved for a unit cell with low insertion loss, the phase shifter is found to be feasible for modern electronically tunable phased arrays used for satellite communication and radar systems.

The purpose of this paper is to discuss two evaluation methods of single pole auto-reclosing process effectiveness in HV transmission lines. Secondary arc current and recovery voltage results obtained by load flow calculation are compared to the results obtained by the time domain simulations. Moreover, a nonlinear secondary arc implementation is presented.

A computer simulation studies were performed using DIgSILENT PowerFactory® software to analyse phenomena during single phase to earth short circuit and during single pole circuit breaker opening. Possibilities of electric arc extinction for different earthing solutions of shunt reactors were examined.

The authors indicate, that precise representation of secondary electric arc in power system studies could lead to different conclusion than analysis carried out on simplified arc models. Recommendations for line construction (i.e. earthing reactor installation) and line operation (i.e. prolongation of dead time during auto-reclosing) based on time domain simulations are less restrictive than resulting from the traditional steady-state calculation approach.

An implementation of mathematical model of nonlinear secondary arc for DIgSILENT PowerFactory® software is presented. The model could be used during the process of design of HV transmission line, to assess its proper operation, to calculate dead time during single pole reclosing or to evaluate the necessity of installing additional earthing reactors.

In recent years, electronic devices have increasingly employed printed circuits produced using electrically conductive adhesives, commonly known as polymer thick films. This method is much more cost‐effective and efficient than other methods of wiring, including those using chemical etching or plating. In the past, the use of metal‐filled polymers as conductors in printed circuit fabrication has suffered from several limitations such as poor solderability, conductivity and adhesion. A new electrically conductive metal‐filled polymer formulation has been developed which overcomes these problems inherent in typical polymer thick film inks. This new product is based on transient liquid‐phase sintering wherein the metallic components of the formulation sinter at a relatively low temperature, resulting in a highly conductive continuous metal network. The sintering is achieved through the interaction of several metallic components with an adhesive‐flux component. The final product is highly conductive, solderable and exhibits excellent adhesion to a wide range of substrate materials. A new process for manufacturing fine‐line printed circuit boards using this ink technology is under investigation. It promises potentially simpler processing and lower cost than plating. In this new process, traces (in the form of troughs in the dielectric) are imaged using conventional photoimageable dielectrics. Exposure and developing conditions depend upon the polymer system used. The transient liquid phase sinterable conductive ink is applied to fill the photo‐exposed conductor pattern. Next, another layer of photoimageable dielectric is applied over the traces and imaged with vias for interconnections with subsequent layers. The dielectric is then cured and the ink applied to fill the vias. These steps may be repeated several times to produce low‐profile fine‐line multilayer printed circuits. This process for producing multilayer circuits using conductive inks simplifies the manufacturing of printed circuits, reduces profile, eliminates most waste in manufacturing, and reduces cost compared with plating.

In the never‐ending quest for speed, designers are now turning to digital GaAs integrated circuits both to extend the bandwidth of current designs and in some cases to generate a whole new class of products never before possible. The engineer well versed in high speed ECL design techniques generally understands the problems associated with this transfer to GaAs logic. However, even with the design task well defined, the exact solution for interconnecting devices is often difficult and stresses the capabilities of existing multilayer printed circuit techniques using conventional dielectric materials and processing. This paper examines the design task in detail, and will present recent developments in shielded discrete wiring techniques as a possible solution for GaAs packaging.

This paper discusses the electromagnetic unbalances of transmission lines caused by mutual impedances. The unbalance factors of 27 different transmission line configurations have been studied by using a digital computer. The impacts of transposition, phase arrangement, additions of transformer, and capacitors to the lines in terms of circulating currents, sequence impedances, and net through and circulatory unbalance factors have been investigated extensively. Furthermore, the impact of “n” overhead ground wires on the electromagnetic unbalance factors of untransposed single‐ and double‐circuit transmission lines have been studied and the results have been tabulated and plotted.

This paper presents the manufacturing methods used in the assembly of electronic circuits with surface mount components on planar printed wiring circuits. The manufacturing process flow is explored as a function of the design of the circuit as well as the selection of surface mount components. Equipment evaluation criteria are presented along with facilities' requirements in the area of utilities and floor space.

The performance of a high‐speed chip is highly dependent on the interconnects, which connect different macro cells within a VLSI chip. Delay, power dissipation and cross‐talk are the major design constraints for high performance VLSI interconnects. The importance of on‐chip inductance is continuously increasing with higher clock frequency, faster on‐chip rise time, wider wires, ever‐growing length of interconnects and introduction of new materials for low resistance interconnects. In the current scenario, interconnect is modeled as an RLC transmission line. Interconnect width optimization plays an important role in deciding transition delay and power dissipation. This paper aims to optimize interconnect width for a matched condition to reduce power and delay parameters.

Width optimization is done for two sets of interconnect terminating conditions, namely active gate and passive capacitance. SPICE simulations have been used to validate the findings.

For a driver interconnect load model terminated by an active gate load, a trade‐off exists between short circuit and dynamic power in inductive interconnects, since with wider lines dynamic power increases, but short circuit power of the load gate decreases due to reduced transient delay. Whereas, for a line terminated by a capacitor, such trade‐off does not exist. Many of the previous researches have modeled the active gate load at the terminating end by its input parasitic gate capacitance.

This paper shows that such modeling leads to inaccuracy in estimation of power, and therefore non‐optimal width selection, especially for large fan‐out conditions.

The finding is that the impedance matching between transmission line at driver and load ends plays an important role in estimation of overall power dissipation and transition delay of a VLSI circuit.

One of the most challenging problems facing the package designer today is how to predict electrical performance before committing a design to fabrication. One means of accomplishing this task is to employ computer‐aided design (CAD) tools that analyse performance from simulations done on models derived from the physical package structures. These models, when combined with the chip models, allow interactive simulation and timing analysis of an entire multilayer package. This paper describes a CAD approach for evaluating interconnect performance within multilayer package structures and presents several examples to show how the approach is applied.