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The purpose of this paper is to assess to what extent intraday data can explain and predict long-term memory.
This article analysed the presence of long-memory volatility in five Asian equity indices, namely, SENSEX, CNIA, NIKKEI225, KO11 and FTSTI, using five-min intraday return series from 05 January 2015 to 06 August 2015 using two approaches, i.e. conditional volatility and realized volatility, for forecasting long-term memory. It employs conditional-generalized autoregressive conditional heteroscedasticity (GARCH), i.e. autoregressive fractionally integrated moving average (ARFIMA)-FIGARCH model and ARFIMA-asymmetric power autoregressive conditional heteroscedasticity (APARCH) models, and unconditional volatility realized volatility using autoregressive integrated moving average (ARIMA) and ARFIMA in-sample forecasting models to estimate the persistence of the long-term memory.
Given the GARCH framework, the ARFIMA-APARCH long-memory model gave the better forecast results signifying the importance of accounting for asymmetric information when modelling volatility in a financial market. Using the unconditional realized volatility results from the Singapore and Indian markets, the ARIMA model outperforms the ARFIMA model in terms of forecast performance and provides reasonable forecasts.
The issue of long memory has important implications for the theory and practice of finance. It is well-known that accurate volatility forecasts are important in a variety of settings including option and other derivatives pricing, portfolio and risk management.
It could be said that using long-memory augmented models would give better results to investors so that they could analyse the market trends in returns and volatility in a more accurate manner and reach at an informed decision. This is useful to minimize the risks.
This research enhances the literature by estimating the influence of intraday variables on daily volatility. This is one of very few studies that uses conditional GARCH framework models and unconditional realized volatility estimates for forecasting long-term memory. The authors find that the methods complement each other.
This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of…
This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm.
Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control.
An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes.
Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.