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Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults. For a pair of response outputs of the circuit under test, the method uses the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits (results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.

The design of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper discusses approach to realizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND, OR/NOR and XOR/XNOR logic, respectively. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.

The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.

In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.

The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.

This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

The design of space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of present day very large-scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). This paper presents an overview of the general problem of designing zero-aliasing or aliasing-free space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) utilizing graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with extensive simulation results on International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM, and COMPACTEST.

Semiconductor devices and systems containing them have become so complex that it is difficult and costly to test them adequately. The solution is to design them to be testable. In this the author considers testability cost trade‐offs, outlines the interrelationship of test programming and designing for testability, and presents several methods of designing for testability.

The purpose of this paper is to disentangle and elaborate on the constitutive elements of the concept of path dependence (initial conditions and lock‐in) for a concerted and in‐depth application to the study of organizational change.

The approach takes the form of a combination of a longitudinal and a comparative case‐study, based on secondary literature.

External initial conditions acted less as “imprinting” forces than is suggested in the literature on the genesis of the Toyota production system (TPS); a firm‐specific philosophy in combination with a critical sequence of events mainly shaped and locked‐in TPS.

The empirical sources are limited to publications in English, so relevant factors explaining the path taken may not all have been included. The importance of a salient meta‐routine might be firm‐specific.

The study contributes to understanding the factors underlying corporate performance by a critical re‐examination of a much heralded production system (TPS).

The paper highlights the use of the concept of meta‐routines to connect the core elements of path dependence, that is, sensitivity to initial conditions and lock‐in mechanisms.

In this work, an efficient architecture for memory built in self-test (MBIST) that incorporates a modified March Y algorithm using concurrent technique and a modified linear feedback shift register (LFSR)–based address generator is proposed.

Built in self-test (BIST) is emerging as the essential ingredient of the system on chip. In the ongoing high speed, high tech sophistication technology of the very large-scale integrated circuits, testing of these memories is a very tedious and challenging job, since the area overhead, the testing time and the cost of the test play an important role.

With the efficient service of the adapted architecture, switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down, the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST.

To improve the yield and fault tolerance of on-chip memories without degradation on its performance self-repair mechanisms can be implemented on chip.

All of us, who are working in this highly interesting field of Avionics, have the same feeling of superiority. We all know that our technology is the heart and soul of today's air transport success. We have enough sense of reality to admit, that in the past, starting with the Wright brothers up to the 1950's, Aviation was dominated by aeronautical engineers. We admit that they really did a good construction job on airframes, wings, engines and so on, but the real thing only started when electronic engineers became interested in Aviation. So in order to prove to those who dispute our growing importance, I thought some trend figures on the rapidly increasing avionics investment percentage, of the basic aircraft purchase price, would be simple and definitely convincing.

Customised executive education, designed for and delivered to individual client companies by Higher Education Institutions (HEIs), differs in important ways from award-bearing courses. One area in which these differences are surprisingly extensive is in the use of technology. We explore the impact of technology-enhanced learning (TEL) on course design, delivery and evaluation of customised executive education. In doing so, we contrast this form of learning with MOOCs, which use TEL in a different way, for a different audience.

We begin with the ‘two-client’ problem. In customised executive programmes, course design is done collaboratively between the HEI and the corporate client, reflecting the particular learning needs of the selected participants as perceived by the commissioning client. We find that the level of TEL in any programme will reflect the learning needs, and also the level of TEL sophistication, of both client and academics.

We then consider the successful integration of TEL into customised executive education. TEL can enrich a course great, but will also mean a loss of academic control, as a significant amount of the learning will be peer-to-peer, and much of the information-gathering can take place outside the classroom.

We conclude with the outcomes and success measures of customised executive education. The institutional disruption of TEL to the HEI is considerable, as their traditional business model is based on rewarding academics for research and for classroom-hours. This needs to be rethought where the classroom element is reduced, but there is constant online interaction with participants.

NOT perhaps the most vintage of Farnboroughs from the point of view of new aircraft and new technology, but undoubtedly one of the most successful in relation to the business done. Some fifteen major orders worth over £32½ million were announced, bringing the total order book for the industry this year to more than £782 million already. This exceeds by a handsome margin the new business won by the industry in any nine‐month period in the past, and it is expected that by the end of the year orders worth well over £800 million will have been received. Highlights of the new British hardware on show were the Hawker Siddeley Nimrod and production Harriers on the military side; the B.A.C. One‐Eleven 500, the Handley Page Jetstream, the Garrett‐engined Short Skyvan, and the Beagle Pups showed the resurgence of the industry's civil interests. The number of foreign aircraft that appeared, sponsored in the main by Rolls‐Royce, bore witness to the strength of Britain's aero engine and aircraft equipment industry, and further evidence of this was found in the exhibition proper with many examples of major items of equipment having been adopted for overseas markets. The overall impression at Farnborough was a new‐found confidence in the future of the industry exemplified by a more aggressive and effective export sales policy that has already proved our ability to deliver the goods. It is not possible to cover all the exhibits shown at Farnborough, but the report following describes many of the interesting items.