Architecture for an efficient MBIST using modified March-y algorithms to achieve optimized communication delay and computational speed
International Journal of Pervasive Computing and Communications
ISSN: 1742-7371
Article publication date: 15 January 2021
Issue publication date: 19 February 2021
Abstract
Purpose
In this work, an efficient architecture for memory built in self-test (MBIST) that incorporates a modified March Y algorithm using concurrent technique and a modified linear feedback shift register (LFSR)–based address generator is proposed.
Design/methodology/approach
Built in self-test (BIST) is emerging as the essential ingredient of the system on chip. In the ongoing high speed, high tech sophistication technology of the very large-scale integrated circuits, testing of these memories is a very tedious and challenging job, since the area overhead, the testing time and the cost of the test play an important role.
Findings
With the efficient service of the adapted architecture, switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down, the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST.
Originality/value
To improve the yield and fault tolerance of on-chip memories without degradation on its performance self-repair mechanisms can be implemented on chip.
Keywords
Citation
O.S., N. and K., S. (2021), "Architecture for an efficient MBIST using modified March-y algorithms to achieve optimized communication delay and computational speed", International Journal of Pervasive Computing and Communications, Vol. 17 No. 1, pp. 135-147. https://doi.org/10.1108/IJPCC-05-2020-0032
Publisher
:Emerald Publishing Limited
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