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The fluctuations that occurred between the power requirements have shown a higher range of voltage regulations and frequency. The fluctuations are caused because of substantial changes in the energy dissipation. The operational efficiency has been reduced when the power grid is enabled with the help of electric vehicles (EVs) that were created by the power resources. The model showed an active load matching for regulating the power and there occurred a harmonic motion in energy. The main purpose of the proposed research is to handle the energy sources for stabilization which has increased the reliability and improved the power efficiency. This study or paper aims to elaborate the security and privacy challenges present in the vehicle 2 grid (V2G) network and their impact with grid resilience.

The smart framework is proposed which works based on Internet of Things and edge computations that managed to perform an effective V2G operation. Thus, an optimum model for scheduling the charge is designed on each EV to maximize the number of users and selecting the best EV using the proposed ant colony optimization (ACO). At the first, the constructive phase of ACO where the ants in the colony generate the feasible solutions. The constructive phase with local search generates an ACO algorithm that uses the heterogeneous colony of ants and finds effectively the best-known solutions widely to overcome the problem.

The results obtained by the existing in-circuit serial programming-plug-in electric vehicles model in terms of power usage ranged from 0.94 to 0.96 kWh which was lower when compared to the proposed ACO that showed power usage of 0.995 to 0.939 kWh, respectively, with time. The results showed that the energy aware routed with ACO provided feasible routing solutions for the source node that provided the sensor network at its lifetime and security at the time of authentication.

The proposed ACO is aware of energy routing protocol that has been analyzed and compared with the energy utilization with respect to the sensor area network which uses power resources effectively.

Deep learning techniques are unavoidable in a variety of domains such as health care, computer vision, cyber-security and so on. These algorithms demand high data transfers but require bottlenecks in achieving the high speed and low latency synchronization while being implemented in the real hardware architectures. Though direct memory access controller (DMAC) has gained a brighter light of research for achieving bulk data transfers, existing direct memory access (DMA) systems continue to face the challenges of achieving high-speed communication. The purpose of this study is to develop an adaptive-configured DMA architecture for bulk data transfer with high throughput and less time-delayed computation.

The proposed methodology consists of a heterogeneous computing system integrated with specialized hardware and software. For the hardware, the authors propose an field programmable gate array (FPGA)-based DMAC, which transfers the data to the graphics processing unit (GPU) using PCI-Express. The workload characterization technique is designed using Python software and is implementable for the advanced risk machine Cortex architecture with a suitable communication interface. This module offloads the input streams of data to the FPGA and initiates the FPGA for the control flow of data to the GPU that can achieve efficient processing.

This paper presents an evaluation of a configurable workload-based DMA controller for collecting the data from the input devices and concurrently applying it to the GPU architecture, bypassing the hardware and software extraneous copies and bottlenecks via PCI Express. It also investigates the usage of adaptive DMA memory buffer allocation and workload characterization techniques. The proposed DMA architecture is compared with the other existing DMA architectures in which the performance of the proposed DMAC outperforms traditional DMA by achieving 96% throughput and 50% less latency synchronization.

The proposed gated recurrent unit has produced 95.6% accuracy in characterization of the workloads into heavy, medium and normal. The proposed model has outperformed the other algorithms and proves its strength for workload characterization.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.