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The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost.

This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture.

This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications.

The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption.

It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce.

Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

This work focused on a basic building block of an allocation unit that carries out the critical job of deciding between the conflicting requests, i.e. an arbiter unit. The purpose of this work is to implement an improved hybrid arbiter while harnessing the basic advantages of a matrix arbiter.

The basic approach of the design methodology involves the extraction of traffic information from buffer signals of each port. As the traffic arrives in the buffer of respective ports, information from these buffers acts as a source of differentiation between the ports receiving low traffic rates and ports receiving high traffic rates. A logic circuit is devised that enables an arbiter to dynamically assign priorities to different ports based on the information from buffers. For implementation and verification of the proposed design, a two-stage approach was used. Stage I comprises comparing the proposed arbiter with other arbiters in the literature using Vivado integrated design environment platform. Stage II demonstrates the implementation of the proposed design in Cadence design environment for application-specific integrated chip level implementation. By using such a strategy, this study aims to have a special focus on the feasibility of the design for very large-scale integration implementation.

According to the simulation results, the proposed hybrid arbiter maintains the advantage of a basic matrix arbiter and also possesses the additional feature of fault-tolerant traffic awareness. These features for a hybrid arbiter are achieved with a 19% increase in throughput, a 1.5% decrease in delay and a 19% area increase in comparison to a conventional matrix arbiter.

This paper proposes a traffic-aware mechanism that increases the throughput of an arbiter unit with some area trade-off. The key feature of this hybrid arbiter is that it can assign priorities to the requesting ports based upon the real-time traffic requirements of each port. As a result of this, the arbiter is dynamically able to make arbitration decisions. Now because buffer information is valuable in winning the priority, the presence of a fault-tolerant policy ensures that none of the priority is assigned falsely to a requesting port. By this, wastage of arbitration cycles is avoided and an increase in throughput is also achieved.

Low-power consumption has become an important issue that cannot be ignored in System-on-Chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. This paper aims at demonstrating an accurate and fast power estimation technique.

The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented Genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure.

The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. In experiments, the average error is estimated at 13.84%.

To present the research findings with clarity and to avoid complexities, the paper does not consider delay factors like glitches, jitter etc. in the power model.

The proposed methodology allowed accurate power/energy analysis of practical applications mapped onto Network-on-Chip (NoC) based Multiprocessors SoC platform. It enables the performance analysis of different design alternatives under the load imposed by complex applications.

This paper is an original contribution and the results demonstrate that our novel technique could be implemented to achieve fast and accurate power estimation in the early stage of any SoC design.

The design of space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of present day very large-scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). This paper presents an overview of the general problem of designing zero-aliasing or aliasing-free space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) utilizing graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with extensive simulation results on International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM, and COMPACTEST.

In this work, an efficient architecture for memory built in self-test (MBIST) that incorporates a modified March Y algorithm using concurrent technique and a modified linear feedback shift register (LFSR)–based address generator is proposed.

Built in self-test (BIST) is emerging as the essential ingredient of the system on chip. In the ongoing high speed, high tech sophistication technology of the very large-scale integrated circuits, testing of these memories is a very tedious and challenging job, since the area overhead, the testing time and the cost of the test play an important role.

With the efficient service of the adapted architecture, switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down, the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST.

To improve the yield and fault tolerance of on-chip memories without degradation on its performance self-repair mechanisms can be implemented on chip.

The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.

An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.

FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm² of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.

The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

In real-time entertainment processing applications, processing of the multiple data streams demands high efficient multiple transfers, which leads to the computational overhead for system-on-chip (SoC), which runs the artificial intelligence algorithms. High-performance direct memory access controller (DMAC) is incorporated in SoC to perform the multiple data transfers without the participation of main processors. But achieving the area-efficient and power-aware DMAC suitable for streaming the multiple data remains to be a daunting challenge among the researchers.

The purpose of this paper to provide the DMA operations without intervention of central processing unit (CPU) for bulk video data transmissions.

The proposed DMAC has been developed based on the hybrid advanced extensible interface (AXI)-PCI bus subsystem to handle the multiple data streams from the video sources. The proposed model consists of bus selector module, user control signal, status register, DMA-supported address and AXI-PCI subsystems to achieve better performance in analysing the video frames.

The extensive experimentation is carried out with Xilinx Zynq SoC architecture using Very High Speed integrated circuit hardware description language (VHDL) programming, and performance metrics such as utilization area and power are calculated and compared with the other existing DMA controllers such as Scatter-DMA, Gather-DMA and Enhanced DMA. Simulation results demonstrate that the proposed DMAC has outperformed other existing DMAC in terms of less area, less delay and power, which makes the proposed model suitable for streaming multiple video streams.

The purpose of this research is to develop a prototype of agent‐based intelligent workflow system for product design collaboration in a distributed network environment.

This research separates the collaborative workflow enactment mechanisms from the collaborative workflow building tools for flexible workflow management. Applying the XML/RDF (resource description framework) ontology schema, workflow logic is described in a standard representation. Lastly, a case study in collaborative system‐on‐chip (SoC) design is depicted to demonstrate the agent‐based workflow system for the design collaboration on the web.

Agent technology can overcome the difficulty of interoperability in cross‐platform, distributed environment with standard RDF data schema. Control and update of workflow functions become flexible and versatile by simply modifying agent reasoning and behaviors.

When business partners want to collaborate, how to integrate agents in different workflows becomes a critical issues.

Agent technology can facilitate design cooperation and teamwork communication in a collaborative, transparent product development environment.

This research establishes generalized flow logic RDF models and an agent‐based intelligent workflow management system, called AWfMS, based on the RDF schema of workflow definition. AWfMS minimizes barriers in the distributed design process and hence increases design cooperations among partners.

The purpose of this study is to locally develop low-cost wireless mesh networks for reliable data communications to devices that prevent the theft of these devices in learning institutions of South Africa.

A network test-bench was developed where millions of packets were transmitted and logged between interconnected nodes to analyze the quality of the network’s service in a harsh indoor building environment. Similar methodologies in “big data” analysis as found in particle physics were adopted to analyze the network’s performance and reliability.

The results from statistical analysis reveal the quality of service between multiple asynchronous transmitting nodes in the network and compared with the wireless technology routing protocol to assess coverage in large geographical areas. The mesh network provides stable data communications between nodes with the exception of reliability degradation in some multi-hopping routes. Conclusions are presented to determine whether the underlining mesh network technology will be deployed to protect devices against theft in educational institutions of South Africa.

The anti-theft application will focus on proprietary firmware development with a reputable tablet manufacturer to render the device inoperable. Data communications of devices to the network will be monitored and controlled from a central management system. The electronics embedding the system-on-chip will be redesigned and developed using the guidelines stipulated by the chip manufacturer.

Design and development of low-cost wireless mesh networks to protect tablets against theft in institutions of digitized learning. The work presents performance and reliability metrics of a low-power wireless mesh wireless technology developed in a harsh indoor building environment.