(2012), "Cadence Palladium XP Verification Computing Platform speeds deployment of Panasonic Systems-on-Chip for digital consumer products", Microelectronics International, Vol. 29 No. 2. https://doi.org/10.1108/mi.2012.21829baa.015
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Copyright © 2012, Emerald Group Publishing Limited
Cadence Palladium XP Verification Computing Platform speeds deployment of Panasonic Systems-on-Chip for digital consumer products
Article Type: New products From: Microelectronics International, Volume 29, Issue 2
Cadence Design Systems, Inc. have announced that Panasonic Corporation has deployed the Cadence Palladium XP Verification Computing Platform, part of the Cadence System Development Suite, to speed the design of Systems-on-Chip (SoCs) for next-generation digital consumer products such as Smart TVs and video recorders. Palladium XP unifies simulation, acceleration and emulation capabilities in a single environment enabling hardware-software system verification. Consequently, customers like Panasonic can rapidly verify their complex SoC designs for cutting-edge consumer products.
Digital consumer products, such as Smart TVs, must support advanced features like multi-channel decoding and display, and Internet access simultaneously. In addition, some functions require software execution, necessitating tight integration between hardware and software.
Using Palladium XP, Panasonic was able to test complex functions and verify hardware-software integration. Specifically, the company was able to connect a validation environment to the Palladium XP system, providing graphic validation capabilities of both hardware and software. The ability to verify its solutions at the system level gives Panasonic confidence it can deliver SoCs for industry-leading digital consumer solutions in tight time-to-market windows.
About Palladium XP
The Cadence Palladium XP Verification Computing Platform is the foundational component of the System Development Suite aimed to reducing the hardware-software system integration time by up to 50 per cent. Palladium XP provides developers a high-fidelity representation of their design so they can quickly and confidently locate and fix bugs, resulting in better-quality systems and subsystems. The platform supports design configurations up to 2 billion gates, delivering performance up to 4 MHz and supporting up to 512 users simultaneously. It also provides unique system-level power analysis to better predict and design consumer electronics. Design teams can “hot swap” simulation with acceleration and emulation in a scalable metric-driven verification environment as needed, which speeds the verification process and enables early access to testing embedded software and evaluating performance implications of different IP and/or system architectures.
Web site: www.cadence.com