Search results

The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost.

This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture.

This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications.

The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption.

It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce.

Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

After more than three decades of research and legal cases pursued by the European Commission (EC) and national regulators, interchange fees for four-party consumer card transactions are capped on December 9, 2015 across the European Union (EU). Since then, the development of card scheme fees has been a raising concern for merchants. Due to their nature, these fees have not been dealt with in research or covered by the Interchange Fee Regulation (IFR). This chapter aims to assess the recent development of card scheme fees within four-party card payment networks by relying on survey data obtained from 104 merchants across the EU. Findings show that for half of the merchant population card scheme fees have increased since the regulation. Further concerns related to transparency of fees, pass-through of savings to retailers and subsequently consumers, and the development of commercial cards are discussed. In light of the EC's scheduled review of the impacts of the policy intervention in 2019 (Article 17 of the IFR), this chapter evaluates alternative arrangements for the setting of card scheme fees with a focus on the legal basis for a potential regulation. Findings shall provide a ground for further interaction between academics, practitioners, and policymakers.

The information explosion had led to the emergence of electronic crime both in the transfer of electronic funds and the gaining of information. Reports on the introduction of the clipper chip to protect information and gives a discription of how it works, giving definitions of various terms. Examines a number of problems associated with the chip: trade; effectiveness; Constitutionality; reliability; necessity. Suggests places of contact for further investigation and information.

This paper suggests using smartcards as Internet nodes, including HTTP servers and client protocols. Because XML is the emerging standard for data syntax, we propose to describe smartcards, cryptographic resources by DTDs, and to access these objects through URLs or XML messages. We underline that according to their computing capacities, smartcards could support classical remote procedure call paradigms (using CGI like mechanisms) or implement trusted proxies performing authentication operations and computing session keys. These components could realise authentication, authorisation and accounting features needed in the next Internet generation. As an illustration we present our work for EAP support in smartcards, the protocol specified by the IEEE forum, for authentication over wired and wireless (802.11) networks.

The continuously increasing need for de‐centralized information systems offering data to the people who need them irrespective of their physical location, as well as the requirement for exchanging information between different but interoperable systems, make the system’s architectural and functional design more complex and in many cases extremely vulnerable in respect to its security attributes. The concept of a “secure portable information file”, that can nowadays be easily implemented through the available smart card technology, can significantly ease information management and ensure maximum data protection in respect to their integrity, confidentiality and availability. This paper presents the use of smart cards in an educational environment as a case‐study example for demonstrating the above mentioned benefits, focussing on the utilization of the smart card’s cryptographic functions for implementing mechanisms capable of providing an extremely secure operational framework in terms of user and application provider authenticity, management of access privileges and data integrity and confidentiality.

Generally, Internet-of-Things (IoT) is quite small sized with limited resource and low cost that may be vulnerable for physical and cloned attacking. All kind of authentication protocols designed to IoT devices are robust despite which it is prone to attack by hackers. In order to resolve this issue, there are various researches that have introduced the best method for obscuring the cryptographic key. However, the studies have majorly aimed to generate the key dynamically from noise data by Fuzzy Extractor (FE) or Fuzzy Commitment (FC). Hence, these methods have utilized this kind of data with noisy source namely Physical Unclonable Function (PUF) or biometric data. There are several IoT devices that get operated over undermined environment in which biometric data is not available but the technique utilized with biometric data can't be used to undermined IoT devices. Even though, the PUF technique is implemented for the undermined IoT devices this is quite vulnerable over physical attacks inclusive of accidental move and theft.

This paper has proposed an advanced scheme in fuzzy commitment over IoT devices which is said to be Improved Two Factor Fuzzy Commitment Scheme (ITFFCS) and this proposed ITFFCS has used two kind of noisy factors present inside and outside the IoT devices. Though, an intruder has accomplished the IoT devices with an access to the internal noisy source, the intruder can't select an exact key from the available data which have been compared using comparable module as an interest.

Moreover, the proposed ITFFC method results are compared with existing Static Random Accessible Memory (SRAM) PUF in enterprises application which illustrated the proposed ITFFC method with PUF has accomplished better results in parameters such as energy consumption, area utilization, False Acceptance Ratio (FAR) and Failure Rejection Ratio (FRR).

Thus, the proposed ITFFCS-PUF is comparatively better than existing method in both FAR and FRR with an average of 0.18% and 0.28%.

Argues that the Clipper chip is an expensive, flawed technology which is being aggressively proposed by the US administration and may permanently erode personal privacy without accomplishing its stated goal. Gives seven reasons why the Clipper chip should be “torpedoed”.

The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.

An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.

FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm² of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.

The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

With the rapid development in wired and wireless networks, the demand for network security system is rising rapidly due to more and more new applications introduced. The main factors that rate the encryption algorithms are its ability to secure and protect data against attacks, its speed and efficiency. In this paper, a reconfigurable network security design using multi-mode data encryption standard (DES) algorithm has been implemented with low complexity and low cost, which will also reduce the speed. The paper aims to discuss these issues.

The design can be easily reconfigured to 3DES (triple DES) which is more secure and more powerful in encryption and decryption, as one of the trick in designing 3DES is to reuse three instances of DES. The design can be used for wired and wireless network applications, and it has been described using VHDL and implemented in a reconfigurable Programmable System-on-Chip (PSoC). The hardware implementation has targeted Xilinx Spartan XC3S700-AN FPGA device.

The main idea of reducing the complexity for the hardware implementation is by optimizing the number of logic gates and LUTs of the design. The number of logic gates can be decreased by changing the way of writing the VHDL code and by optimizing the size of the chip.

The design has been tested in simulation and hardware levels, and the simulation results and performance are discussed.

Digital signatures are only enjoying a gradual and reluctant acceptance, despite the long existence of the relevant legal and technical frameworks. One of the major drawbacks of client‐generated digital signatures is the requirement for effective and secure management of the signing keys and the complexity of the cryptographic operations that must be performed by the signer. Outsourcing digital signatures to a trusted third party would be an elegant solution to the key management burden. Aims to investigate whether this is legally and technically feasible.

In this paper's approach a relying party trusts a Signature Authority (SA) for the tokens it issues, rather than a Certification Authority for the certificates it creates in a traditional public key infrastructure scheme.

The paper argues that passing the control of signature creation to a SA rather than the signer herself, is not a stronger concession than the dependence on an identity certificate issued by a Certification Authority.

The paper proposes a framework for outsourced digital signatures.