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Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits.

In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power.

The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384  mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed.

The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used.

SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array.

The cell can be used for SRAM memory for low power consumptions.

The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.

Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.

This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.

All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

Privacy and security of personal data is the prime concern in any communication. Security algorithms play a crucial role in privacy preserving and are used extensively. Therefore, these algorithms need to be effective as well as energy-efficient. Advanced Encryption Standards (AES) is one of the efficient security algorithms. The principal purpose of this research is to design Energy efficient implementation of AES, as it is one of the important aspects for a step toward green computing.

This paper presents a low voltage complementary metal oxide semiconductor (LVCMOS) based energy efficient architecture for AES encryption algorithm on Field Programmable Gate Array (FPGA) platform. The experiments are performed for five different FPGAs at different input/output standards of LVCMOS. Experiments are performed separately at two frequencies (default and 1.6 GHz).

The comparative study of total on-chip power consumption for different frequency suggested that LVCMOS12 performed best for all the FPGAs. Also, Kintex-7 Low Voltage was found to be the best performing FPGA. At 1.6 GHz frequency, the authors observed 55% less on-chip power consumption when switched from Artix-7 with LVCMOS33 (maximum power consuming combination) to Kintex-7 Low Voltage with LVCMOS12. Mathematical models are developed for the proposed design.

The green implementation of AES algorithm based on LVCMOS standards has not been explored yet by researchers. The energy efficient implementation of AES will certainly be beneficial for society as it will consume less power and dissipate lesser heat to environment.

Purpose: Preserving a country’s culture is crucial for its sustainability. Handicraft is a key draw for tourism destinations; it protects any civilisation’s indigenous knowledge and culture by managing the historical, economic, and ecological ecosystems and perfectly aligns with sustainable development. It has a significant role in creating employment, especially in rural regions and is an essential contributor to the export economy, mainly in developing nations. The study focuses on the skills required and existing gaps in the handicraft industry, its development and prospects by considering women and their role in preserving and embodying the traditional art of making handicrafts.

Approach: A framework has been developed for mapping and analysing the skills required in the handicraft sector using econometric modelling; an enormous number of skills have been crowdsourced from the respondents, and machine learning techniques have been used.

Findings: The findings of the study revealed that employment in this area is dependent not only on general or specialised skills but also on complex matrix skills ranging from punctuality to working in unclean and unsafe environments, along with a set of personal qualities, such as taking initiatives and specific skills, for example polishing and colour coding.

Implications: The skills mapping technique utilised in this study is applicable globally, particularly for women indulged in casual work in developing nations’ handicrafts industry. The sustainable development goals, tourism, and handicrafts are all interconnected. The research includes understanding skills mapping, which provides insights into efficient job matching by incorporating preferences and studying the demand side of casual working by women in the handicraft sector from a skills perspective.

This paper aims to revisit the Indian experience on corporate bankruptcy law to answer “why Indian corporate insolvency law structured differently from a manager-driven (pre-Insolvency Code) to manager-displacing model (post-Insolvency Code)?”

This paper is qualitative in nature. The paper analyses the prevailing theoretical wisdom in corporate insolvency law in India and examines the practices of Indian bankruptcy regime.

The authors argued, considering the corporate ownership composition, the Insolvency and Bankruptcy Code 2016 will not accomplish the intended objective (i.e. the “creditor primacy”). The findings refute with the evolutionary theory, i.e. debt and equity both will tend towards dispersion in outsider system of governance.

This paper put forward the imprint that Indian corporate insolvency regime is manager-displacing under Law on Books and manager-driven under Law on Practice.

This study aims to compare the short-run performance of construction and non-construction initial public offerings (IPOs) that are offered in India during 2006–2015. The study also attempts to investigate the impact of ownership structure (i.e. concentrated ownership in the hand of promoters and institutional ownership) and market sentiment on the performance of construction sector IPOs in short run.

A total of 281 IPOs were listed at National Stock Exchange, India, during the study period, and 44 of those were from construction sector. The short-run performance of these construction and non-construction IPOs was compared using two indicators, i.e. monthly stock return (SR) and excess return over market benchmark (MAR). To examine the effect of concentrated ownership in the hand of promoters, institutional ownership and market sentiment on IPO performance, systematic dynamic panel regression model was developed.

The IPOs of construction firms perform significantly better than the non-construction firms. The performance of construction IPOs is significantly driven by the lag effect. This suggests a significant informational inefficiency, which results in a delayed reaction by investors. The market sentiment has a positive influence on the performance of construction sector IPOs, whereas the institutional holding has a negative influence.

To the best of the author’s knowledge, this study is the first attempt to examine the performance of construction sector IPOs in short run. The study uses systematic dynamic panel data regression, which provides better and reliable estimates.