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Article
Publication date: 10 September 2019

Shilpi Birla

Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though…

Abstract

Purpose

Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits.

Design/methodology/approach

In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power.

Findings

The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384  mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed.

Research limitations/implications

The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used.

Practical implications

SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array.

Social implications

The cell can be used for SRAM memory for low power consumptions.

Originality/value

The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

Details

Circuit World, vol. 45 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 11 October 2018

Mitesh Jethabhai Limachia, Rajesh A. Thakker and Nikhil J. Kothari

This paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to…

Abstract

Purpose

This paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.

Design/methodology/approach

A new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.

Findings

The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.

Originality/value

The proposed bit-cell is novel compared with existing bit-cells.

Details

Circuit World, vol. 44 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 17 June 2021

Alok Kumar Mishra, Vaithiyanathan D., Yogesh Pal and Baljit Kaur

This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used…

Abstract

Purpose

This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell.

Design/methodology/approach

The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate.

Findings

Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively.

Originality/value

The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

Details

Circuit World, vol. 48 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 18 November 2021

Kumar Neeraj, Mohammed Mahaboob Basha and Srinivasulu Gundala

Smart ubiquitous sensors have been deployed in wireless body area networks to improve digital health-care services. As the requirement for computing power has drastically…

Abstract

Purpose

Smart ubiquitous sensors have been deployed in wireless body area networks to improve digital health-care services. As the requirement for computing power has drastically increased in recent years, the design of low power static RAM-based ubiquitous sensors is highly required for wireless body area networks. However, SRAM cells are increasingly susceptible to soft errors due to short supply voltage. The main purpose of this paper is to design a low power SRAM- based ubiquitous sensor for healthcare applications.

Design/methodology/approach

In this work, bias temperature instabilities are identified as significant issues in SRAM design. A level shifter circuit is proposed to get rid of soft errors and bias temperature instability problems.

Findings

Bias Temperature Instabilities are focused on in recent SRAM design for minimizing degradation. When compared to the existing SRAM design, the proposed FinFET-based SRAM obtains better results in terms of latency, power and static noise margin. Body area networks in biomedical applications demand low power ubiquitous sensors to improve battery life. The proposed low power SRAM-based ubiquitous sensors are found to be suitable for portable health-care devices.

Originality/value

In wireless body area networks, the design of low power SRAM-based ubiquitous sensors are highly essential. This design is power efficient and it overcomes the effect of bias temperature instability.

Details

International Journal of Pervasive Computing and Communications, vol. 17 no. 5
Type: Research Article
ISSN: 1742-7371

Keywords

Article
Publication date: 24 August 2021

Kumar Neeraj and Jitendra Kumar Das

High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in…

Abstract

Purpose

High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.

Design/methodology/approach

Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.

Findings

Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.

Originality/value

The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

Details

International Journal of Intelligent Unmanned Systems, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 2049-6427

Keywords

Article
Publication date: 23 March 2020

Pramod Kumar Patel, M.M. Malik and Tarun Kumar Gutpa

The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate…

Abstract

Purpose

The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.

Design/methodology/approach

This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.

Findings

The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.

Research limitations/implications

Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.

Practical implications

GNRFET devices are suitable for implementing low power and high density SRAM cell.

Social implications

The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.

Originality/value

This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

Details

Circuit World, vol. 46 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

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